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a) Design a CMOS logic circuit to realize the following function Y = A¯B¯C + A¯BC¯ + AB¯C¯ by constructing both the Pull Up Network (PUN) and Pull Down Network (PDN). [6 points] b) Provide the W/L ratios for each transistor in the logic circuit obtained in a). Assume that for the basic inverter n = 2, p = 4 and L = 0.5 μm. [3 points ] c) Design a pass-transistor-logic circuit (transmission gate) to realize the function Y¯ = AB + A¯B¯. [3 points] d) Define the following parameters; and find them from the shown VTC [3 points ] i) VIH ii) VIL iii) NML iv) NMH

a) Design a CMOS logic circuit to realize the following function Y = A¯B¯C + A¯BC¯ + AB¯C¯ by constructing both the Pull Up Network (PUN) and Pull Down Network (PDN). [6 points] b) Provide the W/L ratios for each transistor in the logic circuit obtained in a). Assume that for the basic inverter n = 2, p = 4 and L = 0.5 μm. [3 points ] c) Design a pass-transistor-logic circuit (transmission gate) to realize the function Y¯ = AB + A¯B¯. [3 points] d) Define the following parameters; and find them from the shown VTC [3 points ] i) VIH ii) VIL iii) NML iv) NMH

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a) Design a CMOS logic circuit to realize the following function Y = A ¯ B ¯ C + A ¯ B C ¯ + A B ¯ C ¯ by constructing both the Pull Up Network (PUN) and Pull Down Network (PDN). [6 points] b) Provide the W / L ratios for each transistor in the logic circuit obtained in a). Assume that for the basic inverter n = 2 , p = 4 and L = 0.5 μ m . [ 3 points ] c) Design a pass-transistor-logic circuit (transmission gate) to realize the function Y ¯ = A B + A ¯ B ¯ . [ 3 points] d) Define the following parameters; and find them from the shown VTC [ 3 points ] i) V I H ii) V I L iii) N M L iv) N M H

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(i) Design a CMOS logic circuit to implement the function Y = AB + C¯. Find the minimum width for each transistor such that the delay is not worse than the reference inverter. Assume that for the basic inverter n = 2 and p = 4 and that technology used is L = 0.5 μm. ( 8 marks) (ii) Consider the circuit shown below. (a) Express Y as a function of A and B. (b) Redraw the circuit using CMOS Transmission gate switch. (c) Compare the performance of the Transmission Gate switch to the NMOS switch and PMOS switch. (6 marks) (iii) Mark the correct answer in the following. (6 marks)VIH is a) the maximum input voltage level to be considered as High. b) the maximum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the minimum input voltage level to be considered as Low. VIL is a) the maximum input voltage level to be considered as High. b) the minimum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the maximum input voltage level to be considered as Low. The noise margin in the Low state for a logical circuit with VIH = 2.2 V, VIL = 0.4 V, VOH = 4.0 V and VOL = 0.2 V is a) 0.2 V. b) 2.0 V c) 1.8 V. d) 3.6 V.

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