A DRAM cell uses a storage capacitor of 38 fF, VDD = 2.5 V and VT = 0.

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A DRAM cell uses a storage capacitor of 38 fF, VDD = 2.5 V and VT = 0.5 V for the NMOS access FET. If the bit line capacitance is 454 fF, the sense amp can detect voltages down to 28 mV as a valid one, and the memory is refreshed every 9 μsec, what is the maximum leakage current that can be tolerated in nanoamps? The correct answer is 6.9

A DRAM cell uses a storage capacitor of 38 fF, VDD = 2.5 V and VT = 0.5 V for the NMOS access FET. If the bit line capacitance is 454 fF, the sense amp can detect voltages down to 28 mV as a valid one, and the memory is refreshed every 9 μsec, what is the maximum leakage current that can be tolerated in nanoamps? The correct answer is 6.9

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A DRAM cell uses a storage capacitor of

38 f F, V D D = 2.5 V

and

V T = 0.5 V

for the NMOS access FET. If the bit line capacitance is

454 f F

, the sense amp can detect voltages down to

28 m V

as a valid one, and the memory is refreshed every

9 μ s e c

, what is the maximum leakage current that can be tolerated in nanoamps?

The correct answer is 6.9

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