a) Figure Q3 shows an nMOS inverter consisting of a depletion n-channel load (ML) with an enhancement n-channel driver (MD). With the aid of fully labelled and superimposed output characteristics of both devices, briefly describe the operation of the inverter. Figure Q3 b) The inverter in 3a) is to be designed (i. e. find suitable channel widths and channel lengths of MD and ML) to generate an output voltage of 0.2 V for a logic 0 . The supply voltage, VDD is 5 V, the threshold voltages of the load and driver transistors are −2 V and 1 V respectively. Prove any assumptions made. c) Sketch a possible layout of your design in 3b), assuming both the minimum feature size λm and maximum alignment accuracy λa to be 0.5 μm. Make sure to include the alignment error and utilise minimal area. d) Assume the device constant of ML is 1.8×10−4 A/V, calculate the maximum d. c. power dissipation of the inverter.