(a) Given inputs A, B, C, A
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![[25%] In the following Domino logic circuit, VDD = 2 V. There are parasitic capacitances of 10 fF, 10 fF, 40 fF, 20 fF and 60 fF at nodes 1, 2, 3, 4 and Y, respectively. All the NMOS transistors have an ON -resistance of 10 kΩ and a threshold voltage of 0.43 V. (a) Express X and Y as Boolean functions of inputs A, B, C, D, and E. (b) The CMOS inverter between the two dynamic gates is essential. Why? (c) How would you set the relative driving strength of the NMOS and PMOS in this inverter? Explain. (d) Consider A = B = 1 and C changing from 0 to 1 during the evaluation phase (clk is high). Estimate the propagation delay from C to node 3 using the Elmore model. (e) The above inputs come together with E = D = 0, and node 4 is initially discharged. What is the voltage at Y at the end of the evaluation phase?](https://www.doubtrix.com/uploads/editor/3531945024OKyzrjLccy.png)
