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A NMOS only inverter Figure 3 shows the design of an inverter with NMOS only. a. Simulate the maximum and minimum voltages at Vout . What's the corresponding Vin for them? b. Plot out the VTC. c. Compare this design with the CMOS inverter. What are the main disadvantages?

A NMOS only inverter Figure 3 shows the design of an inverter with NMOS only. a. Simulate the maximum and minimum voltages at Vout . What's the corresponding Vin for them? b. Plot out the VTC. c. Compare this design with the CMOS inverter. What are the main disadvantages?

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  1. A NMOS only inverter Figure 3 shows the design of an inverter with NMOS only. a. Simulate the maximum and minimum voltages at V out . What's the corresponding V in for them? b. Plot out the VTC. c. Compare this design with the CMOS inverter. What are the main disadvantages?

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CMOS inverter design Figure 2 shows the design of a CMOS inverter. WN = 420 nm and WP = 504 nm. CL = 20 fF, which is added in the test bench, not in the schematic. a. Plot out the voltage transfer characteristic (VTC), which is the curve of Vout vs. Vin , when Vin sweeps from 0 to VDD. b. Apply a ramp input to Vin , which is a 0 to VDD switching, with the transition time Tr = 30 ps (as shown in Figure 2). Plot out the waveform of Vout. Measure the 50% VDD delay (i. e. , time Figure 2. The schematics of a CMOS inverter difference from the 50% point of input to the 50% point of output) and the time for Vout to transit from 90%−10%VDD .

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