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A three-input CMOS NAND gate is designed as shown below. Assume that VDD=1.2 V, K'n = 90 uA/V2, Vtn = 0.4 V, K'p = 50 uA/V2, and Vtp=-0.5 V in the 100nm technology node. Determine the width of NMOS and PMOS transistors in this NAND gate, such that the worst case delay becomes equivalent to a referenced inverter with Wn=1um and Wp=2um. For the device sizes found in part (a), determine the switching threshold voltage, VM, when all inputs are tied together. Find the maximum IDD current for this NAND gate.

A three-input CMOS NAND gate is designed as shown below. Assume that VDD=1.2 V, K'n = 90 uA/V2, Vtn = 0.4 V, K'p = 50 uA/V2, and Vtp=-0.5 V in the 100nm technology node. Determine the width of NMOS and PMOS transistors in this NAND gate, such that the worst case delay becomes equivalent to a referenced inverter with Wn=1um and Wp=2um. For the device sizes found in part (a), determine the switching threshold voltage, VM, when all inputs are tied together. Find the maximum IDD current for this NAND gate.

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A three-input CMOS NAND gate is designed as shown below. Assume that VDD=1.2 V, K'n = 90 uA/V2, Vtn = 0.4 V, K'p = 50 uA/V2, and Vtp=-0.5 V in the 100nm technology node. Determine the width of NMOS and PMOS transistors in this NAND gate, such that the worst case delay becomes equivalent to a referenced inverter with Wn=1um and Wp=2um. For the device sizes found in part (a), determine the switching threshold voltage, VM, when all inputs are tied together. Find the maximum IDD current for this NAND gate.

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a) Find the logic expression for Z. What function does this circuit implement?

b) Draw the pull-up network that completes the CMOS logic circuit.

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d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit.

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