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(b) For the pass-transistor circuits shown below, answer the following questions 1 - 4. Assume VDD, GND as power supplies and |Vtp| and Vtn as the threshold voltages of pMOS and nMOS respectively. In the above figure, the output voltage for the pass-transistor circuit in (a) is In the above figure, the output voltage for the pass-transistor circuit in (b) is In the above figure, the output voltage for the pass-transistor circuit in (c) is In the above figure, the output voltage for the pass-transistor circuit in (d) is A 2-input NOR gate is designed to achieve the effective rise and fall time of a unit inverter. What is the value of k for the pMOS transistors? What is the value of k for the nMOS transistor in the 2 -input NOR gate in the above problem?

(b) For the pass-transistor circuits shown below, answer the following questions 1 - 4. Assume VDD, GND as power supplies and |Vtp| and Vtn as the threshold voltages of pMOS and nMOS respectively. In the above figure, the output voltage for the pass-transistor circuit in (a) is In the above figure, the output voltage for the pass-transistor circuit in (b) is In the above figure, the output voltage for the pass-transistor circuit in (c) is In the above figure, the output voltage for the pass-transistor circuit in (d) is A 2-input NOR gate is designed to achieve the effective rise and fall time of a unit inverter. What is the value of k for the pMOS transistors? What is the value of k for the nMOS transistor in the 2 -input NOR gate in the above problem?

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(b)
For the pass-transistor circuits shown below, answer the following questions 1 - 4. Assume VDD, GND as power supplies and |Vtp| and Vtn as the threshold voltages of pMOS and nMOS respectively.
  1. In the above figure, the output voltage for the pass-transistor circuit in (a) is
  2. In the above figure, the output voltage for the pass-transistor circuit in (b) is
  3. In the above figure, the output voltage for the pass-transistor circuit in (c) is
  4. In the above figure, the output voltage for the pass-transistor circuit in (d) is
  5. A 2-input NOR gate is designed to achieve the effective rise and fall time of a unit inverter. What is the value of k for the pMOS transistors?
  6. What is the value of k for the nMOS transistor in the 2 -input NOR gate in the above problem?

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