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b) Size the transistors in this gate so that the worst-case on resistance for the pull-up and pull-down networks are the same as that for the static CMOS inverter. c) Size the transistors in this gate so that the best-case on resistance for the pull-up and pull-down networks are the same as that for the static CMOS inverter.

b) Size the transistors in this gate so that the worst-case on resistance for the pull-up and pull-down networks are the same as that for the static CMOS inverter. c) Size the transistors in this gate so that the best-case on resistance for the pull-up and pull-down networks are the same as that for the static CMOS inverter.

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b) Size the transistors in this gate so that the worst-case on resistance for the pull-up and pull-down networks are the same as that for the static CMOS inverter. c) Size the transistors in this gate so that the best-case on resistance for the pull-up and pull-down networks are the same as that for the static CMOS inverter.

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