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(b) The pMOS inverter above, contains one pMOS enhancement mode and one pMOS depletion mode transistor. You may assume that for a logic low input that both transistors are operating in their non-saturation mode. Calculate the voltage swing for this pMOS inverter, where VDD = 1.8 V, the enhancement threshold is exactly Vt = −0.4 V and the depletion threshold is exactly Vtd = 1.0 V, for the following pull-down (depletion) to pullup (enhancement) ratios: (i) 4:1 (ii) 8:1 You may assume that the input originates from a standard 8:1 pMOS inverter (i. e. an inverter with one enhancement mode and one depletion mode transistor).

(b) The pMOS inverter above, contains one pMOS enhancement mode and one pMOS depletion mode transistor. You may assume that for a logic low input that both transistors are operating in their non-saturation mode. Calculate the voltage swing for this pMOS inverter, where VDD = 1.8 V, the enhancement threshold is exactly Vt = −0.4 V and the depletion threshold is exactly Vtd = 1.0 V, for the following pull-down (depletion) to pullup (enhancement) ratios: (i) 4:1 (ii) 8:1 You may assume that the input originates from a standard 8:1 pMOS inverter (i. e. an inverter with one enhancement mode and one depletion mode transistor).

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(b)
The pMOS inverter above, contains one pMOS enhancement mode and one pMOS depletion mode transistor. You may assume that for a logic low input that both transistors are operating in their non-saturation mode. Calculate the voltage swing for this pMOS inverter, where V D D = 1.8 V , the enhancement threshold is exactly V t = − 0.4 V and the depletion threshold is exactly V t d = 1.0 V , for the following pull-down (depletion) to pullup (enhancement) ratios: (i) 4 : 1 (ii) 8 : 1
You may assume that the input originates from a standard 8:1 pMOS inverter (i.e. an inverter with one enhancement mode and one depletion mode transistor).

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