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c). What is the static value of Y in volts when A = 0 V and B = 2.5 V for the circuit shown in Fig. 1c below? Fig. 1c d). When comparing the logic circuit of Fig. 1c to a CMOS logic circuit implementing a 2-input NAND function, which circuit would result in a smaller physical area assuming equal current drive capability (matched design)?

c). What is the static value of Y in volts when A = 0 V and B = 2.5 V for the circuit shown in Fig. 1c below? Fig. 1c d). When comparing the logic circuit of Fig. 1c to a CMOS logic circuit implementing a 2-input NAND function, which circuit would result in a smaller physical area assuming equal current drive capability (matched design)?

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c). What is the static value of Y in volts when A = 0 V and B = 2.5 V for the circuit shown in Fig. 1c below? Fig. 1c d). When comparing the logic circuit of Fig. 1c to a CMOS logic circuit implementing a 2-input NAND function, which circuit would result in a smaller physical area assuming equal current drive capability (matched design)?

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a). What is the value of Y in volts when A = 0 V and B = 5.0 V for the circuit shown in Fig. 1a below? b). When comparing the logic circuit of Fig. 1a (in part a) to a CMOS Logic Circuit implementing a 2-input NOR function, which circuit would result in a smaller physical area assuming equal current drive capability (matched design) and why?
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Charge sharing is an important problem in dynamic circuits. Switching exposes a fixed amount of charge to a different capacitive environment. This results in node voltage change. After pre-charge stage, the output node voltage of the dynamic logic circuit in Figure 1 will be equal to VDD. During the evaluate phase, assume A = 1 and B=0. Output node will not connect to ground but the total charge on the output node (Q = C.V) will be shared by parasitic capacitance (C1) and the load capacitance (CL). So that the output voltage will drop and be equal to M1 source voltage. a. The circuit is Figure 1 is pre-charged with VDD = 3V. During evaluation stage, M1 turns on and M2 is off (A=1 and B=0). CL = 250fF, C1 = 125fF and Vt0,n=0.55V. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? b. Repeat question a for C1 = 40fF. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? If not, what is the value of the output voltage at this scenario? c. With A = 1 and B = 0, the output of the circuit in Fig 1 should be logic high. However, you have seen that logic high does not mean VDD for this example. Output voltage depends on the parasitic capacitance at the source node of M2. For a dynamic 2 input NAND gate, what is the maximum value that the Figure 1 output voltage can reach when A= 1 and B = 0?

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Consider the CMOS logic circuit shown in Fig. P9.7, which is a simple domino circuit. Node X is connected to a CMOS inverter so that the output of the inverter can be directly fed to the next stage of the domino circuit. a. Explain how the voltage level at node X, after it is precharged to 1.2 V, can be affected by the charge sharing between node X and node Y if their node capacitances are the same. Express the final voltage at node X in terms of the initial voltage at node Y when the charge sharing is completed, following the full precharge operation when the gate terminal of transistor M2 is fixed at 0 V. b. Determine the ratio between device transconductance parameters, kp and kn, of the inverter to prevent any logic error due to charge sharing between nodes X and Y under all circumstances. Assume that the magnitudes of threshold voltages in the inverter are equal to 0.45 V. The use of Level 1 transistor current equations is deemed adequate.

Consider the CMOS logic circuit shown in Fig. P9.7, which is a simple domino circuit. Node X is connected to a CMOS inverter so that the output of the inverter can be directly fed to the next stage of the domino circuit. a. Explain how the voltage level at node X, after it is precharged to 1.2 V, can be affected by the charge sharing between node X and node Y if their node capacitances are the same. Express the final voltage at node X in terms of the initial voltage at node Y when the charge sharing is completed, following the full precharge operation when the gate terminal of transistor M2 is fixed at 0 V. b. Determine the ratio between device transconductance parameters, kp and kn, of the inverter to prevent any logic error due to charge sharing between nodes X and Y under all circumstances. Assume that the magnitudes of threshold voltages in the inverter are equal to 0.45 V. The use of Level 1 transistor current equations is deemed adequate.

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