Cascode Stage. Design a Cascode amplifier shown in figure below to ach

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Cascode Stage. Design a Cascode amplifier shown in figure below to achieve a gain of 1600. Assume VDD = 1 V, Vth = 0.3 V, λn = 0.2 V−1, γ = 0, μnCox = 100 μA/V2, I1 = 1 mA, gmro ≫ 1. a) Find bias point (VGS−Vth of transistors) to achieve the target gain such that we achieve maximum swing at Vout. b) Find W/L for each transistor. c) Calculate optimal Vb and VIN DC bias to maximize output swing. What is this maximum/minimum voltage levels at the output? What is the maximum swing? d) Notice you must generate a specific Vb externally to maximize the swing. If a lazy designer decides to connect Vb to VDD instead, what would be the swing in this case? e) To realize the current source load, we will use a PMOS active load. For PMOS, use the same parameters with λp = 0.2 V−1, μpCox = 50 μA/V2. Assume the bias current will remain at 1mA, find the new gain value. What would be the W/L for PMOS if we want to have a VOD(VGS−Vth) of 0.1V for this device. f) Repeat part (e) for a PMOS load with 2L gate length. g) It seems like making the PMOS load very large (large W) is beneficial to reduce VOD and consequently improving the voltage swing. What do you think is the drawback?

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Cascode Stage. Design a Cascode amplifier shown in figure below to achieve a gain of 1600. Assume $V D D = 1 V, V_{t h} = 0.3 V, λ_{n} = 0.2 V^{- 1}, γ = 0, μ_{n} C_{o x} = \frac{100 μ A}{V^{2}}, I_{1} =$ $1 m A, g_{m} r_{o} ≫ 1$ . a) Find bias point $(V_{G S} - V_{th}$ of transistors) to achieve the target gain such that we achieve maximum swing at $V_{out}$ . b) Find W/L for each transistor. c) Calculate optimal $V_{b}$ and $V_{IN} D C$ bias to maximize output swing. What is this maximum/minimum voltage levels at the output? What is the maximum swing? d) Notice you must generate a specific $V_{b}$ externally to maximize the swing. If a lazy designer decides to connect $V_{b}$ to VDD instead, what would be the swing in this case? e) To realize the current source load, we will use a PMOS active load. For PMOS, use the same parameters with $λ_{p} =$ $0.2 V^{- 1}, μ_{p} C_{o x} = \frac{50 μ A}{V^{2}}$ . Assume the bias current will remain at $1 m A$ , find the new gain value. What would be the W/L for PMOS if we want to have a $V_{O D} (V_{G S} - V_{t h})$ of $0.1 V$ for this device. f) Repeat part (e) for a PMOS load with 2L gate length. g) It seems like making the PMOS load very large (large W) is beneficial to reduce $V_{O D}$ and consequently improving the voltage swing. What do you think is the drawback?