Question

Notify Me Bookmark

Chapter 6, problem 7: For each of the following circuits, complete the timing diagram for the state of each flip flop and the output, where shown. All flip flops are trailing-edge triggered. For those circuits in which there is no clear input, assume each flip flop starts at 0. (a) Chapter 6, problem 8: For the following circuit and input string: Show a timing trace for the flip-flops and the output as far as possible. Assume that the initial value of each flip flop is 0.

Chapter 6, problem 7: For each of the following circuits, complete the timing diagram for the state of each flip flop and the output, where shown. All flip flops are trailing-edge triggered. For those circuits in which there is no clear input, assume each flip flop starts at 0. (a) Chapter 6, problem 8: For the following circuit and input string: Show a timing trace for the flip-flops and the output as far as possible. Assume that the initial value of each flip flop is 0.

Image text
Chapter 6, problem 7: For each of the following circuits, complete the timing diagram for the state of each flip flop and the output, where shown. All flip flops are trailing-edge triggered. For those circuits in which there is no clear input, assume each flip flop starts at 0 . (a)
Chapter 6, problem 8: For the following circuit and input string: Show a timing trace for the flip-flops and the output as far as possible. Assume that the initial value of each flip flop is 0 . a)

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

For the following circuit: a. Is this a Moore or Mealy model (5 points)? b. Write the flip flop input and next state equations (20 points), c. Write the output equation (5 points) d. Complete a state table for the circuit ( 20 points) e. Complete the timing trace as far as possible (20 points) (Assume both flip-flops are connected to a shared clock.)
Solution
0 0

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.
Solution
0 0

SRAM (static random access memory): This problem concerns the design of a 4-resistor 2-transistor (BJT) SRAM cell (flip-flop) having a supply voltage of VCC = 5.0 V. Assume that the BJT's CE saturation voltage (VCE,sat) in the ON state is 0.2 V. Assume that the current amplification of the transistors is β = 50. (a) Draw the circuit diagram. (b) Choose one of the two stable states of the flip-flop, and indicate all circuit elements that consume power. Circle these circuit elements. (c) Write an equation for the power consumed by each of these circuit elements (circled under the previous question). Sum up all these powers (summands) to obtain the total power consumed by the circuit. Which of these summands represents the greatest power? Give the approximate power consumed by the circuit by writing an equation that has just the dominant summand. (d) Design a 4-resistor 2-transistor SRAM circuit in which the dominant power-consuming circuit element consumes a power of about 1 μW. What is the collector current? Suggest numerical values for the resistances of all four resistors. (e) What would be the power consumed by a 1 Gbit SRAM circuit using the memory cell you just designed? Do you have any comments on the result?
Solution
0 0