Question

Notify Me Bookmark

CMOS Inverter. Consider the CMOS inverter circuit shown below. Neglect channel length modulation effects (λ = 0) and assume you place a load resister RL at the output. Intuitively plot the transfer function (Vout vs. Vin) you expect to see while varying Vin from 0 to VDD.

CMOS Inverter. Consider the CMOS inverter circuit shown below. Neglect channel length modulation effects (λ = 0) and assume you place a load resister RL at the output. Intuitively plot the transfer function (Vout vs. Vin) you expect to see while varying Vin from 0 to VDD.

Image text
CMOS Inverter. Consider the CMOS inverter circuit shown below. Neglect channel length modulation effects ( λ = 0 ) and assume you place a load resister R L at the output. Intuitively plot the transfer function ( V out v s . V in ) you expect to see while varying V in from 0 to V D D .

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

Consider the CMOS inverter circuit with a capacitor connected at its output as shown below. Here Kn′ = 2 mA/V2 and VTn = 1.5 V, Kp′ = 1 mA/V2 and VTp = −0.5 V, all MOSFETs have L = 1 μm, and remember that K = K′(W/L). For a MOSFET in triode, use the S-R model with RON = 1 /K(|VGS| − |VT| ) (works for both nFET and pFET). a) Design Wp and Wn such that the overall circuit threshold, VTH, occurs at VDD/2 as shown in the graph. Here you can assume that at the threshold point VIN = VOUT = VTH. Use the smallest integer values you can for Wp and Wn, assuming the minimum width allowed is 1 μm. b) When VIN = VDD, draw the equivalent circuit. What is the time constant? c) When VIN = 0, draw the equivalent circuit. What is the time constant? d) Based on your answers from (b) and (c), which transition do you expect to be fastest: when vOUT transitions from VDD to 0 V, or when vOUT transitions from 0 V to VDD ? Why?
Solution
0 0

Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3 Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3

Solution
0 0

Consider the following amplifier operating at 300 K. The transistor M1 has μnCox = 250 μA/V2 and Vth = 0.4V. You may assume that M1 operates in saturation region and neglect its channel length modulation (λ = 0). The supply voltage VDD is 1.8V. (a) Find the expression for the input resistance (Rin) assuming that M1 has the transconductance of gm in saturation region. (b) Find the expression for the voltage gain AV=Vout /vin. (c) Explain the phase relationship between the vin and Vout signals. In other words, are they in phase or out of phase? Explain the reason why. (d) If this amplifier stage must provide an output resistance of 500 Ω, what is the maximum allowable value for ID of M1 that keeps M1 in saturation? (e) For the ID value obtained from (d), calculate the required value of W/L that makes the voltage gain Av equal to 10. (f) Calculate the maximum load capacitance (Cout ) that the amplifier can drive at its output while keeping its −3dB bandwidth above 100 MHz.
Solution
0 0