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(CMOS inverter) (total: 40 pts) Considering the following CMOS inverter circuit with long-channel ideal n/p MOSFET and voltage transfer characteristics, (a) Derive the VIL and VIH equation and show that NML = NMH if βn = βp and Vth, n = |Vth,p| (8 pts) (Note: βn = μnCoxWn/Ln, βp = μpCoxWp/Lp and assume body-effect coefficient 'm' is 1)

(CMOS inverter) (total: 40 pts) Considering the following CMOS inverter circuit with long-channel ideal n/p MOSFET and voltage transfer characteristics, (a) Derive the VIL and VIH equation and show that NML = NMH if βn = βp and Vth, n = |Vth,p| (8 pts) (Note: βn = μnCoxWn/Ln, βp = μpCoxWp/Lp and assume body-effect coefficient 'm' is 1)

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  1. (CMOS inverter) (total: 40 pts) Considering the following CMOS inverter circuit with long-channel ideal n / p MOSFET and voltage transfer characteristics, (a) Derive the V I L and V I H equation and show that N M L = N M H if β n = β p and V t h , n = | V t h , p | ( 8 p t s ) (Note: β n = μ n C o x W n L n , β p = μ p C o x W p L p and assume body-effect coefficient ' m ' is 1)

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Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].

Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].
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a) For the CMOS inverter shown below, calculate and plot the dc quasi-static current that flows through the transistor as a function of 0 ≤ VIN ≤ VDD. Given: VDD = 5 V For n-MOSFET: μnCOX = 20 μA/V2 W/L = 2 and Vth, n = 1 V For p-MOSFET: μpCOX = 10 μA/V2 W/L = 4 and |Vth,p| = 1 V Where Vth,n and Vth,p are threshold voltages of n-and p-MOSFETs. L and W are channel length and gate width of the MOSFET. μ is the mobility of carriers in the channel region. COX is the gate gate oxide capacitance /area. MOSFET I-V Relations: ID = 0.5 μCOX(W/L){2(VGS−Vth)VDS−VDS2} (Linear region) ID = 0.5 μCox(W/L){(VGS−Vth)2} (Saturation region) Where VGS is the gate-to-source voltage and ID is the drain current. b) Compute dynamic power dissipation if now a square wave input with time period TP is applied to input. Given CL = 0.01 pF and TP = 100 ns.

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(i) Design a CMOS logic circuit to implement the function Y = AB + C¯. Find the minimum width for each transistor such that the delay is not worse than the reference inverter. Assume that for the basic inverter n = 2 and p = 4 and that technology used is L = 0.5 μm. ( 8 marks) (ii) Consider the circuit shown below. (a) Express Y as a function of A and B. (b) Redraw the circuit using CMOS Transmission gate switch. (c) Compare the performance of the Transmission Gate switch to the NMOS switch and PMOS switch. (6 marks) (iii) Mark the correct answer in the following. (6 marks)VIH is a) the maximum input voltage level to be considered as High. b) the maximum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the minimum input voltage level to be considered as Low. VIL is a) the maximum input voltage level to be considered as High. b) the minimum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the maximum input voltage level to be considered as Low. The noise margin in the Low state for a logical circuit with VIH = 2.2 V, VIL = 0.4 V, VOH = 4.0 V and VOL = 0.2 V is a) 0.2 V. b) 2.0 V c) 1.8 V. d) 3.6 V.

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