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(CMOS inverter) (total: 40 pts) Considering the following CMOS inverter circuit with long-channel ideal n/p MOSFET and voltage transfer characteristics, (a) Derive the VIL and VIH equation and show that NML = NMH if βn = βp and Vth, n = |Vth,p| (8 pts) (Note: βn = μnCoxWn/Ln, βp = μpCoxWp/Lp and assume body-effect coefficient 'm' is 1)

(CMOS inverter) (total: 40 pts) Considering the following CMOS inverter circuit with long-channel ideal n/p MOSFET and voltage transfer characteristics, (a) Derive the VIL and VIH equation and show that NML = NMH if βn = βp and Vth, n = |Vth,p| (8 pts) (Note: βn = μnCoxWn/Ln, βp = μpCoxWp/Lp and assume body-effect coefficient 'm' is 1)

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  1. (CMOS inverter) (total: 40 pts) Considering the following CMOS inverter circuit with long-channel ideal n / p MOSFET and voltage transfer characteristics, (a) Derive the V I L and V I H equation and show that N M L = N M H if β n = β p and V t h , n = | V t h , p | ( 8 p t s ) (Note: β n = μ n C o x W n L n , β p = μ p C o x W p L p and assume body-effect coefficient ' m ' is 1)

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In the following CMOS inverter logic gate, assume the transistor size of (W/L)n = 0.8 μm/0.20 μm and (W/L)p = 1.6 μm/0.20 μm and VDD = 3.0 V. (a). Determine the operation modes (e. g. cut-off, linear or saturation) of the NMOS and PMOS transistors respectively at Vin = 0.2 V, 0.9 V, 1.5 V, 2.1 V, and 2.8 V. Using a table to list the operation modes is recommended. (Note: You may need to do multiple calculations for the data point Vin = 1.5 V with Vin = 1.4 V or 1.6 V). (b). Using the tabulated results in (a) or otherwise, determine the current flowing through both the NMOS and PMOS transistors at the different input voltage Vin in (a). (c). Using Matlab or Excel, plot a graph of the current against the input voltage Vin. (d). Using the above results in (a) and (b) or otherwise, determine the output voltage Vout at the different input voltage Vin in (a). (e). Using Matlab or Excel, plot a graph of the voltage transfer characteristics (VTC) (i. e. output voltage Vout versus input voltage Vin ) of the CMOS inverter with the five sets of data points obtained. It is given that the threshold voltage VTon = 0.50 V and μnCox = 430 μA/V2 for the NMOS transistor while VTop = −0.50 V and μpCox = 210 μA/V2 for the PMOS transistor. Assume the long-channel approximation of the MOSFET and there is no body effect (i. e. the body terminal of the MOSFETs are properly connected respectively to ground and VDD).
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Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].

Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].
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a) For the CMOS inverter shown below, calculate and plot the dc quasi-static current that flows through the transistor as a function of 0 ≤ VIN ≤ VDD. Given: VDD = 5 V For n-MOSFET: μnCOX = 20 μA/V2 W/L = 2 and Vth, n = 1 V For p-MOSFET: μpCOX = 10 μA/V2 W/L = 4 and |Vth,p| = 1 V Where Vth,n and Vth,p are threshold voltages of n-and p-MOSFETs. L and W are channel length and gate width of the MOSFET. μ is the mobility of carriers in the channel region. COX is the gate gate oxide capacitance /area. MOSFET I-V Relations: ID = 0.5 μCOX(W/L){2(VGS−Vth)VDS−VDS2} (Linear region) ID = 0.5 μCox(W/L){(VGS−Vth)2} (Saturation region) Where VGS is the gate-to-source voltage and ID is the drain current. b) Compute dynamic power dissipation if now a square wave input with time period TP is applied to input. Given CL = 0.01 pF and TP = 100 ns.

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