Consider a SRAM cache system with L1, L2, and L3 caches, perform the timing analysis using the following information. Assume L1 intrinsic access time t1 = 2 clock cycles, L1 cache miss rate is 0.1 , and L2 intrinsic access time t2 = 4 clock cycles, L2 cache miss rate is 0.05, and L3 intrinsic access time t3 = 10 clock cycles, and assume all the data could be found from L3 cache. Please calculate L1 perceived access time T1 [5 pts]
![Consider a SRAM cache system with L1, L2, and L3 caches, perform the timing analysis using the following information. Assume L1 intrinsic access time t1 = 2 clock cycles, L1 cache miss rate is 0.1 , and L2 intrinsic access time t2 = 4 clock cycles, L2 cache miss rate is 0.05, and L3 intrinsic access time t3 = 10 clock cycles, and assume all the data could be found from L3 cache. Please calculate L1 perceived access time T1 [5 pts]](https://www.doubtrix.com/uploads/editor/8670227984rjLikylZRh.png)
