Consider Mirror Adder circuit below: (a) Size NMOS and PMOS devices in the circuit so that the worst-case pull-up and pull-down strength of the circuit is exactly as much as in an inverter. Assume that all the transistors in the circuit and in the inverter have a minimum channel length (LMIN). In the inverter, the width of NMOS is WMIN and PMOS is 2 × WMIN. You can mention sizes in the figure itself. (b) How can you resize transistors from your solution in (a) to make the circuit faster? You are not allowed to increase the total area of your circuit.

Consider Mirror Adder circuit below: (a) Size NMOS and PMOS devices in the circuit so that the worst-case pull-up and pull-down strength of the circuit is exactly as much as in an inverter. Assume that all the transistors in the circuit and in the inverter have a minimum channel length (LMIN). In the inverter, the width of NMOS is WMIN and PMOS is 2 × WMIN. You can mention sizes in the figure itself. (b) How can you resize transistors from your solution in (a) to make the circuit faster? You are not allowed to increase the total area of your circuit.

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Consider Mirror Adder circuit below: (a) Size NMOS and PMOS devices in the circuit so that the worst-case pull-up and pull-down strength of the circuit is exactly as much as in an inverter. Assume that all the transistors in the circuit and in the inverter have a minimum channel length (LMIN). In the inverter, the width of NMOS is WMIN and PMOS is 2 × WMIN. You can mention sizes in the figure itself. (b) How can you resize transistors from your solution in (a) to make the circuit faster? You are not allowed to increase the total area of your circuit.

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