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Consider the circuit given in the following figure. Assume that all NMOS transistors have an equivalent ON resistance Rn and all PMOS transistors have an equivalent ON resistance Rp. a) Write the equation for high to low propagation delay (tpHL) at the output of 4-input NAND gate using Elmore delay model. b) Write the equation for low to high propagation delay (tpLH) at the output of 4-input NAND gate assuming all inputs switching from logic high to logic low.

Consider the circuit given in the following figure. Assume that all NMOS transistors have an equivalent ON resistance Rn and all PMOS transistors have an equivalent ON resistance Rp. a) Write the equation for high to low propagation delay (tpHL) at the output of 4-input NAND gate using Elmore delay model. b) Write the equation for low to high propagation delay (tpLH) at the output of 4-input NAND gate assuming all inputs switching from logic high to logic low.

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Consider the circuit given in the following figure. Assume that all NMOS transistors have an equivalent ON resistance Rn and all PMOS transistors have an equivalent ON resistance Rp. a) Write the equation for high to low propagation delay (tpHL) at the output of 4-input NAND gate using Elmore delay model. b) Write the equation for low to high propagation delay (tpLH) at the output of 4-input NAND gate assuming all inputs switching from logic high to logic low.

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For the gate shown below, assume the equivalent resistance of NMOS and PMOS transistors are Rn = 10 kΩ and Rp = 20 kΩ, respectively, and an equal junction capacitance of 0.1 fF for W L = 1. Ignore channel length modulation, and any other capacitances, but do not ignore the internal node junction capacitances. a. (2) What function is implemented by this circuit? b. (2) Size the transistors for equal worst case pull-up and pull-down resistances. c. (6) Devise a stick diagram representing the circuit layout. d. (8) Find the input patterns that give the worst-case low-to-high propagation delay (tpLH), and find this delay. e. (8) Redo part d for the worst-case high-to-low propagation delay (tpHL) f. (6) Calculate the logical effort for each of the inputs, and the gate parasitic delay. g. (6) Estimate the activity factor, αY0→1, for the output F, if P(A = 1) = P(B = 1) = P(C = 1) = 1/2. What is the energy dissipated for 0→1 transition? Assume VDD = 1 V, and for this part only, a total capacitance of 1 fF at output only.
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Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.
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Consider the circuit shown below, having an output F and inputs A and B. Suppose that all NMOS transistors are identical and all PMOS transistors are identical. Equivalent resistor for an NMOS transistor: RN = 8 kohm Equivalent resistor for a PMOS transistor: Rp = 24 kohm Suppose that each circuit node (Hint: output node and the node between transistors having A and B inputs) has an equivalent capacitance value of 1pF. Calculate the worst-case propagation delays, tPLH and tPHL (total of 2 values).
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