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Consider the circuit in Fig P3.3-6. It is a series connection of n MOSFET transistors. Each transistor has the same width, W, but each transistor can have a different length, L. Derive an expression for W and L for a single transistor that replaces, and is equivalent to, the multiple series transistors. When using the simple model, you must ignore body effect.

Consider the circuit in Fig P3.3-6. It is a series connection of n MOSFET transistors. Each transistor has the same width, W, but each transistor can have a different length, L. Derive an expression for W and L for a single transistor that replaces, and is equivalent to, the multiple series transistors. When using the simple model, you must ignore body effect.

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Consider the circuit in Fig P3.3-6. It is a series connection of n MOSFET transistors. Each transistor has the same width, W, but each transistor can have a different length, L. Derive an expression for W and L for a single transistor that replaces, and is equivalent to, the multiple series transistors. When using the simple model, you must ignore body effect.

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Consider the circuit in Fig P3.3-5. It is a parallel connection of n MOSFET transistors. Each transistor has the same length, L, but each transistor can have a different width, W. Derive an expression for W and L for a single transistor that replaces, and is equivalent to, the multiple parallel transistors.
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Consider a DRAM cell that uses an internal capacitor of 20 fF; it is charged to 3.3 V when storing a ' 1 '. In this problem, ignore body effect. (A real transistor like the access transistor here, or pass transistors in switch logic, can turn off before you want it to because of body effect; this one stays on until the 20 fF capacitor is fully charged. ) (6-points) (a) When writing a ' 1 ', how long does it take for the voltage on the capacitor to rise to 95% of its final value? Assume that when it is on, the access transistor in the cell has an average resistance of 6 kΩ; assume that the inverter driving the bit line has an average pull-up resistance of 1 kΩ. Ignore the resistance and capacitance of the bit line itself. (In a real memory, wire parasitics play a big role!)? (b) Suppose that when reading, the bit line is first charged to 3.3 V. The bit line is a large piece of metal, and has a total capacitance of 500 fF. How far does the bit line drop in voltage if a ' 0 ' is read? (Hint: In circuits, you learned that charge on capacitors in parallel redistributes until the voltage is equal; assume enough time is given for the bit line to drop as far as it ever will. )? (c) Suppose that the leakage current from the cell, due to the reverse-biased diode and subthreshold MOSFET currents, is no more than 2 pA. If a signal loss on the capacitor of 0.5 V can be tolerated, how often must the DRAM cell be refreshed to ensure that no data is lost?

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Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].

Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].
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