Question

Notify Me Bookmark

Consider the circuit shown below, having an output F and inputs A and B. Suppose that all NMOS transistors are identical and all PMOS transistors are identical. Equivalent resistor for an NMOS transistor: RN = 8 kohm Equivalent resistor for a PMOS transistor: Rp = 24 kohm Suppose that each circuit node (Hint: output node and the node between transistors having A and B inputs) has an equivalent capacitance value of 1pF. Calculate the worst-case propagation delays, tPLH and tPHL (total of 2 values).

Consider the circuit shown below, having an output F and inputs A and B. Suppose that all NMOS transistors are identical and all PMOS transistors are identical. Equivalent resistor for an NMOS transistor: RN = 8 kohm Equivalent resistor for a PMOS transistor: Rp = 24 kohm Suppose that each circuit node (Hint: output node and the node between transistors having A and B inputs) has an equivalent capacitance value of 1pF. Calculate the worst-case propagation delays, tPLH and tPHL (total of 2 values).

Image text
Consider the circuit shown below, having an output F and inputs A and B. Suppose that all NMOS transistors are identical and all PMOS transistors are identical. Equivalent resistor for an NMOS transistor: RN = 8 kohm Equivalent resistor for a PMOS transistor: Rp = 24 kohm Suppose that each circuit node (Hint: output node and the node between transistors having A and B inputs) has an equivalent capacitance value of 1pF. Calculate the worst-case propagation delays, tPLH and tPHL (total of 2 values).

Detailed Answer

1 0

Please enter your email here. You will get email when this question is answered by our tutor.

Answer
Doubtrix Logo

This Problem has been solved!

You'll get a detailed, step-by-step and expert verified solution.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Login Sign Up
  • Student Reviews:
  • (1)

Similar/Related Questions

Consider the circuit shown below. Suppose that all NMOS transistors are identical and all PMOS transistors are identical. Equivalent resistor for an NMOS transistor: RN = 8kohm Equivalent resistor for a PMOS transistor: RP = 24kohm Suppose that each circuit node (including outputs) has a capacitance value of 1pF. a) Derive a Boolean expression for the output F in terms of the inputs A and B. b) Calculate the worst-case and the best-case propagation delays, tPLH and tPHL values (total of 4 values).
Solution
1 0

In the dynamic logic circuit shown below, all the transistors have the minimum channel length, and their sizes (widths) are marked. The inverter at the output is a standard static CMOS inverter with a PMOS size of 2 and an NMOS size of 1 . For a unit-sized NMOS or PMOS transistor, the intrinsic capacitance at its drain or source terminal is CD, and the capacitance at its gate is CG. For unit-sized NMOS and PMOS transistors, their onresistances are RN and RP, respectively. CD = CG = 1 fF and RP = 2 RN = 2 kΩ. (a) Express y as a Boolean function of the inputs A, B, C and D in the evaluation phase (CLK = 1). (b) Find the capacitances at nodes y, a, b and c, respectively. (c) Let A = B = D = 1 and C = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase (CLK = 0). Estimate the time it takes for the voltage at y to decrease from VDD to VDD/2 in the evaluation phase. (d) Repeat (c) if nodes a, b and c are at VDD in the pre-charge phase. (e) If the inputs are C = 1 and A = B = D = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase. Considering the charge sharing effect, what is the voltage at node y in the evaluation phase? It is known VDD = 2.5 V, VTN = 0.5 V and the body effect of the transistors can be ignored.

Solution
0 0

For the gate shown below, assume the equivalent resistance of NMOS and PMOS transistors are Rn = 10 kΩ and Rp = 20 kΩ, respectively, and an equal junction capacitance of 0.1 fF for W L = 1. Ignore channel length modulation, and any other capacitances, but do not ignore the internal node junction capacitances. a. (2) What function is implemented by this circuit? b. (2) Size the transistors for equal worst case pull-up and pull-down resistances. c. (6) Devise a stick diagram representing the circuit layout. d. (8) Find the input patterns that give the worst-case low-to-high propagation delay (tpLH), and find this delay. e. (8) Redo part d for the worst-case high-to-low propagation delay (tpHL) f. (6) Calculate the logical effort for each of the inputs, and the gate parasitic delay. g. (6) Estimate the activity factor, αY0→1, for the output F, if P(A = 1) = P(B = 1) = P(C = 1) = 1/2. What is the energy dissipated for 0→1 transition? Assume VDD = 1 V, and for this part only, a total capacitance of 1 fF at output only.
Solution
0 0