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Consider the CMOS inverter circuit below where k′n(W/L) = k′p(W/L) with (W/L)n = 20, (W/L)p = 40. K′n = 2 k′p = 20 μA/V2, Vt = |Vtp| = 1 V, C = 69.2 fF and VDD = 5 V. a) What is Vth? b) Draw the transfer characteristic in voltage c) Determine tp, tPHL and tPLH

Consider the CMOS inverter circuit below where k′n(W/L) = k′p(W/L) with (W/L)n = 20, (W/L)p = 40. K′n = 2 k′p = 20 μA/V2, Vt = |Vtp| = 1 V, C = 69.2 fF and VDD = 5 V. a) What is Vth? b) Draw the transfer characteristic in voltage c) Determine tp, tPHL and tPLH

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Consider the CMOS inverter circuit below where k ′ n ( W / L ) = k ′ p ( W / L ) with ( W / L ) n = 20 , ( W / L ) p = 40 . K ′ n = 2 k ′ p = 20 μ A / V 2 , V t = | V t p | = 1 V , C = 69.2 f F and V D D = 5 V . a) What is Vth? b) Draw the transfer characteristic in voltage c) Determine tp, tPHL and tPLH

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You have to fabricate a CMOS inverter in the latest 3-nm technology (L = 3 nm), for which VDD = 1.3 V, Vtn = |Vtp| = 0.4 V, (W/L)n = 5, and kn′ = 4.2kp′ = 450 mA/V2. a) Find the Noise Margins and total area for the following conditions: i. Match case (kn = kp) ii. Wp = 2.1Wn b) Which condition would you choose between the two previous and explain why? c) Find the dynamic power if you know that the total equivalent capacitance at the output will be C = 15 fF and you are required to operate the inverter at f = 2.6 GHz. d) For the case when (W/L)p = 2.1(W/L)n, find the propagation times ( tPHL, tPLH and tp). Assume again C = 15 fF.

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For the amplifier below, following design information is provided: VDD = 3.3 V, R = 2.4 kΩ, ISS = 1.8 mA, k1 = k2 = 5 mA/V2, VTH,1 = VTH,2 = 0.5 V, λ = 0.1 V−1, γ = 0, ki′ = μ0Cox, ki = μ0 Cox(W L)i. Assume that both transistors are identical and in the saturation region. Finally, NMOS and PMOS bulk terminals are connected to the ground and VDD, respectively. a) What is the DC bias voltage for M1 and M2 given that the voltage drop across ISS is 0.4 V ? You can neglect the channel length modulation, here. Check that the transistors are in the correct operation-mode. b) The resistors will be realized using identical PMOS transistors M3 and M4. If the transistors to be used will have k3 = k4 = 1.5 mA/V2, what will be their overdrive voltages? Check that the transistors are in the correct operation-mode. c) What is the differential voltage gain AV,diff = Vout/Vid in dB ? d) ISS will be realized as a cascode current source. Assume that the voltage drop of 0.4 V is equally shared by the two transistors, M5 and M6 having k5′ = k6′ = 0.5 mA/V2 and VTH, 5 = VTH, 6 = 0.5 V. Assuming the gate voltages of both transistors are 1 V, find the W/L ratios of each device. Once again, you can neglect the channel length modulation here. e) Considering (d), how would the W/L ratios qualitatively change (increase/decrease/stays the same), if γ > 0 ? Explain your reasoning analytically, i. e. , using appropriate equations. f) Using the cascode current source, calculate the common-mode gain of the circuit AV, CM = Vout /Vin in dB, where Vin . s applied to the gates of both M1 and M2. Assume λ = 0.1 V−1 for M5 and M6. g) Calculate the CMRR of the circuit in dB.
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The transmission gate of Fig. 18.7 is fabricated in a CMOS process technology for which = 450 μA/V2, = 150 μA/V2, Vtn = |Vtp|, Vt0 = 0.35 V, γ = 0.25 V1/2, 2ϕf = 1.0 V, and VDD = 1 V. Let QN and QP have dimensions (W/L)n = (W/L)p = 130 nm/65 nm. The total capacitance at the output node is 5 fF. Use as many of the results of Example 18.1 as you need. (a) What are the values of VOH and VOL? (b) For the situation in Fig. 18.7(a), find iDN(0), iDP(0), iDN(tPLH), iDP(tPLH), and tPLH. (c) For the situation depicted in Fig. 18.7(b), find iDN(0), iDP(0), iDN(tPHL), iDP(tPHL), and tPHL. At what value of vO will QP turn off? (d) Find tP. (a)

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