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Consider the CMOS inverter circuit to the right. Vtn = |Vtp| = 0.5 V, Vdd = 1.8 V, kn= 2 mA/V^2, kp = 1 mA/V2. If Vin = 0.9 V find Vout and the current through both transistors. Be sure to pay attention to the differences in the two transistors.

Consider the CMOS inverter circuit to the right. Vtn = |Vtp| = 0.5 V, Vdd = 1.8 V, kn= 2 mA/V^2, kp = 1 mA/V2. If Vin = 0.9 V find Vout and the current through both transistors. Be sure to pay attention to the differences in the two transistors.

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Consider the CMOS inverter circuit to the right. Vtn = |Vtp| = 0.5 V, Vdd = 1.8 V, kn= 2 mA/V^2, kp = 1 mA/V2. If Vin = 0.9 V find Vout and the current through both transistors. Be sure to pay attention to the differences in the two transistors.

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Figure 4-1 shows a CMOS logic inverter driving a capacitive load of 100pF. The input to the inverter is a clock signal Vin switching between 0 and 5 V. Several parameters for both the PMOS and NMOS devices are also given. NOTE: The process parameters for the devices are NOT equal! a) Using a simple resistor-switch model for the MOSFETS, determine the propagation delays tPLH (low-to-high output transition) and tPHL (high-to-low output transition) for this CMOS inverter. Please indicate any assumptions that apply. b) For the given input signal VIN, carefully sketch the output voltage across the capacitor as a function of time on the graph provided. NOTE: Be sure to indicate the propagation delays on the graph. c) If two PMOS devices are connected in parallel (for M1), which propagation delay will be affected and what will its new value be? M1: P-Channel Wp = 160 μm Lp = 25 μm kp’ = 100 μA/V2 |Vtp| = 1.85 V M2: N-Channel Wn = 160 μm Ln = 25 μm kn’ = 150 μA/V2 Vtn = 1.85 V

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