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Consider the CMOS SRAM cell in the figure during the read operation. Assume that Q = 1, and bit lines are precharged to VDD/2. Ignore the body effect. Process parameters: VDD = 5 V, VTN = -VTP = 1 V, KN = 120 μA/V2, KP = 40 μA/V2, CB = 50 pF. Assuming M5 and M6 drain currents to be constant with initial values, how long (ns) will it take to develop 25mV differential voltage difference between the bit lines? Choose the closest value. a. 0.5 b. 5 c. 1 d. 2 e. 4

Consider the CMOS SRAM cell in the figure during the read operation. Assume that Q = 1, and bit lines are precharged to VDD/2. Ignore the body effect. Process parameters: VDD = 5 V, VTN = -VTP = 1 V, KN = 120 μA/V2, KP = 40 μA/V2, CB = 50 pF. Assuming M5 and M6 drain currents to be constant with initial values, how long (ns) will it take to develop 25mV differential voltage difference between the bit lines? Choose the closest value. a. 0.5 b. 5 c. 1 d. 2 e. 4

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Consider the CMOS SRAM cell in the figure during the read operation. Assume that Q = 1, and bit lines are precharged to VDD/2. Ignore the body effect. Process parameters: VDD = 5 V, VTN = -VTP = 1 V, KN = 120 μA/V2, KP = 40 μA/V2, CB = 50 pF. Assuming M5 and M6 drain currents to be constant with initial values, how long (ns) will it take to develop 25mV differential voltage difference between the bit lines? Choose the closest value. a. 0.5 b. 5 c. 1 d. 2 e. 4

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