Consider the following circuit Inverter timing: Propagation delay tp = 20 pS Flip-Flop timing: Setup time tsu = 30 pS Hold time thold = 10 ps Clock-to-Q delay tclk- = 50 pS Assume the CLK signal has a square waveform with 50% duty cycle. a. Draw the waveforms of signals CLK, D, and Q for 4 clock cycles. b. What is the ratio between the oscillation frequency of the signals CLK and Q ? c. For this circuit to operate correctly, determine the maximum CLK frequency based on the given timing characteristics of the flip-flop and the inverter. d. Would a hold time violation occur on the flip-flop at any CLK frequency? Why or why not? e. If this circuit dissipates 100 Micro-Watts when operating at Vdd = 2.5 Volts and CLK frequency of 1 GHz, estimate the power dissipation of the circuit when operating at Vdd = 1.25 V and CLK frequency of 100 MHz. Assume the power dissipation is dominated by the switching (dynamic) power. (1 GHz = 109 Hz and 1 MHz = 106 Hz)
