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Consider the following common source amplifier with a current mirror load Assume the following process parameters: VDD = 3.3 V Vtn = ∣Vtp∣ = 0.5 V kn′ = 5 mA/V2 kp′ = 3.2 mA/V2 You are now told that IREF = 500 μA and (W/L)Q1 = 10, (W/L)Q2 = 10, (W/L)Q3 = 5. Assume all transistors are in saturation. Find the DC bias current, ID. (Ignore the Early effect). Find the transconductance of Q1, gm1. (Ignore the Early effect).

Consider the following common source amplifier with a current mirror load Assume the following process parameters: VDD = 3.3 V Vtn = ∣Vtp∣ = 0.5 V kn′ = 5 mA/V2 kp′ = 3.2 mA/V2 You are now told that IREF = 500 μA and (W/L)Q1 = 10, (W/L)Q2 = 10, (W/L)Q3 = 5. Assume all transistors are in saturation. Find the DC bias current, ID. (Ignore the Early effect). Find the transconductance of Q1, gm1. (Ignore the Early effect).

Consider the following common source amplifier with a current mirror load Assume the following process parameters: VDD = 3.3 V Vtn = ∣Vtp∣ = 0.5 V kn′ = 5 mA/V2 kp′ = 3.2 mA/V2 You are now told that IREF = 500 μA and (W/L)Q1 = 10, (W/L)Q2 = 10, (W/L)Q3 = 5. Assume all transistors are in saturation. Find the DC bias current, ID. (Ignore the Early effect). Find the transconductance of Q1, gm1. (Ignore the Early effect).

Consider the following common source amplifier with a current mirror load Assume the following process parameters: VDD = 3.3 V Vtn = ∣Vtp∣ = 0.5 V kn′ = 5 mA/V2 kp′ = 3.2 mA/V2 You are now told that IREF = 500 μA and (W/L)Q1 = 10, (W/L)Q2 = 10, (W/L)Q3 = 5. Assume all transistors are in saturation. Find the DC bias current, ID. (Ignore the Early effect). Find the transconductance of Q1, gm1. (Ignore the Early effect).

 

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Consider the following common source amplifier with a current mirror load Assume the following process parameters: VDD = 3.3 V Vtn = ∣Vtp∣ = 0.5 V kn′ = 5 mA/V2 kp′ = 3.2 mA/V2 You are now told that IREF = 500 μA and (W/L)Q1 = 10, (W/L)Q2 = 10, (W/L)Q3 = 5. Assume all transistors are in saturation. Find the DC bias current, ID. (Ignore the Early effect). Find the transconductance of Q1, gm1. (Ignore the Early effect).

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A. (3 pts) Find the DC bias current, ID. (Ignore the Early effect). B. (3 pts) Find the transconductance of Q1, gm1. (Ignore the Early effect). C. (4 pts) What is the lowest possible output voltage v0 where Q1 still remains in saturation? (Ignore the Early effect). D. (4 pts) Given voltage gain, AV, = -40 V/V and VAn= |VAp|, find VAn. (Hint, output resistances r01 and r02 are equal). Given NMOS integrated common source amplifier below, with parameters as listed, answer the following questions. Make sure to show your work and answers on work paper, including the answer with units, and put a box around the final answers. Only your work paper will be graded. Assume all transistors are in saturation.

A. (3 pts) Find the DC bias current, ID. (Ignore the Early effect). B. (3 pts) Find the transconductance of Q1, gm1. (Ignore the Early effect). C. (4 pts) What is the lowest possible output voltage v0 where Q1 still remains in saturation? (Ignore the Early effect). D. (4 pts) Given voltage gain, AV, = -40 V/V and VAn= |VAp|, find VAn. (Hint, output resistances r01 and r02 are equal). Given NMOS integrated common source amplifier below, with parameters as listed, answer the following questions. Make sure to show your work and answers on work paper, including the answer with units, and put a box around the final answers. Only your work paper will be graded. Assume all transistors are in saturation.

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For the amplifier below, following design information is provided: VDD = 3.3 V, R = 2.4 kΩ, ISS = 1.8 mA, k1 = k2 = 5 mA/V2, VTH,1 = VTH,2 = 0.5 V, λ = 0.1 V−1, γ = 0, ki′ = μ0Cox, ki = μ0 Cox(W L)i. Assume that both transistors are identical and in the saturation region. Finally, NMOS and PMOS bulk terminals are connected to the ground and VDD, respectively. a) What is the DC bias voltage for M1 and M2 given that the voltage drop across ISS is 0.4 V ? You can neglect the channel length modulation, here. Check that the transistors are in the correct operation-mode. b) The resistors will be realized using identical PMOS transistors M3 and M4. If the transistors to be used will have k3 = k4 = 1.5 mA/V2, what will be their overdrive voltages? Check that the transistors are in the correct operation-mode. c) What is the differential voltage gain AV,diff = Vout/Vid in dB ? d) ISS will be realized as a cascode current source. Assume that the voltage drop of 0.4 V is equally shared by the two transistors, M5 and M6 having k5′ = k6′ = 0.5 mA/V2 and VTH, 5 = VTH, 6 = 0.5 V. Assuming the gate voltages of both transistors are 1 V, find the W/L ratios of each device. Once again, you can neglect the channel length modulation here. e) Considering (d), how would the W/L ratios qualitatively change (increase/decrease/stays the same), if γ > 0 ? Explain your reasoning analytically, i. e. , using appropriate equations. f) Using the cascode current source, calculate the common-mode gain of the circuit AV, CM = Vout /Vin in dB, where Vin . s applied to the gates of both M1 and M2. Assume λ = 0.1 V−1 for M5 and M6. g) Calculate the CMRR of the circuit in dB.
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Question 2. (25 points) Assume the following current mirror. Q1 and Q2 are matched. Answer the following questions. A. (5 points) Assuming Q2 is in saturation, when does the output resistance of Q2, (ro2), affect the current Io? Explain your answer. B. (5 points) Assume both transistors are in saturation and operate at Vov = 0.5 V, Vt = 0.5 V, VDD = 5 V, kn′ = 800 μA/V2, (W/L)Q1 = (W/L)Q2 = 10, and |VA2| = |VA1|. What is VGS? C. (5 points) Given the assumptions in part B, what is IREF? (You can ignore channel-length modulation)
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