Question

Notify Me Bookmark

Consider the open-loop circuit (on the left) and closed-loop circuit (on the right) shown in Figure 1 below. In this problem, the open-loop circuit (on the left) will be used to analyze the open-loop behavior of the closed-loop circuit (on the right). closed - loof ciruit Figure 1. Open-loop (left) and closed-loop (right) circuits for Problem 1. Here are the problem parameters:The NMOS devices have gmn = 6 mA/V and rdsn = 25 kΩ. The PMOS devices have gmp = 3 mA/V and rdsp = 15 kΩ. Resistor values are R1 = 1 kΩ and R2 = 3 kΩ. a) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop gain Av. OL = Vout /Vin . For the purposes of this analysis, as we have done a million times before (reminder: this is the 2 nd semester of electronics, so this should not be your first electronics rodeo), you should deactivate all sources in the circuit, except Vin. . b) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop output resistance Rout, oL. , i. e. , the resistance seen looking in at the output node Vout. . You should deactivate all sources in the circuit; feel free to add an appropriate test source(s), if you think you need to do that. c) Referring to the open-loop circuit of Figure 1, determine the numerical loop gain from the test source to the output node: LG = |Vout /Vtest | For the purposes of this analysis, you should deactivate all sources in the circuit, except Vtest. . Also, note that the way the loop gain is defined, it will be a positive-valued quantity. Explain why we want to use a positive loop gain for determining the closed-loop performance [see, e. g. , parts (d) and (e) below]. Your answer for this part should be both i) specific to this problem and ii) generalized to any closed-loop circuit with negative feedback. You are strongly encouraged to consider incorporating a generalized block diagram to help strengthen your argument(s). d) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop gain Av, CL = Vout /Vin . Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop gain, you should instead utilize the results of the previous parts to determine Av, cL. Here, I need to remind you that you should do as you have been (hopefully) doing on the previous parts: first, state the equation you will use to determine Av, cL in terms of, e. g. , Av. ol. and/or Rout, ol and/or LG (i. e. , resist the temptation to dive straight into the numerical values, but feel free to write your equation in terms of Av, ol and/or Rout, ol. and/or LG instead of gmn, gmp, rdsn, rdpp , R1, R2 ), and then plug the numbers in to your equation, and then box your numerical answer along with all the things that we have expected of your numerical quantities since day one. Make it really easy for me to find the equation you used (same story for all of the parts of this problem). e) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop output resistance Rout, CL. Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop output resistance, you should instead follow the same guidance that was given for part (d) of this problem.

Consider the open-loop circuit (on the left) and closed-loop circuit (on the right) shown in Figure 1 below. In this problem, the open-loop circuit (on the left) will be used to analyze the open-loop behavior of the closed-loop circuit (on the right). closed - loof ciruit Figure 1. Open-loop (left) and closed-loop (right) circuits for Problem 1. Here are the problem parameters:The NMOS devices have gmn = 6 mA/V and rdsn = 25 kΩ. The PMOS devices have gmp = 3 mA/V and rdsp = 15 kΩ. Resistor values are R1 = 1 kΩ and R2 = 3 kΩ. a) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop gain Av. OL = Vout /Vin . For the purposes of this analysis, as we have done a million times before (reminder: this is the 2 nd semester of electronics, so this should not be your first electronics rodeo), you should deactivate all sources in the circuit, except Vin. . b) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop output resistance Rout, oL. , i. e. , the resistance seen looking in at the output node Vout. . You should deactivate all sources in the circuit; feel free to add an appropriate test source(s), if you think you need to do that. c) Referring to the open-loop circuit of Figure 1, determine the numerical loop gain from the test source to the output node: LG = |Vout /Vtest | For the purposes of this analysis, you should deactivate all sources in the circuit, except Vtest. . Also, note that the way the loop gain is defined, it will be a positive-valued quantity. Explain why we want to use a positive loop gain for determining the closed-loop performance [see, e. g. , parts (d) and (e) below]. Your answer for this part should be both i) specific to this problem and ii) generalized to any closed-loop circuit with negative feedback. You are strongly encouraged to consider incorporating a generalized block diagram to help strengthen your argument(s). d) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop gain Av, CL = Vout /Vin . Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop gain, you should instead utilize the results of the previous parts to determine Av, cL. Here, I need to remind you that you should do as you have been (hopefully) doing on the previous parts: first, state the equation you will use to determine Av, cL in terms of, e. g. , Av. ol. and/or Rout, ol and/or LG (i. e. , resist the temptation to dive straight into the numerical values, but feel free to write your equation in terms of Av, ol and/or Rout, ol. and/or LG instead of gmn, gmp, rdsn, rdpp , R1, R2 ), and then plug the numbers in to your equation, and then box your numerical answer along with all the things that we have expected of your numerical quantities since day one. Make it really easy for me to find the equation you used (same story for all of the parts of this problem). e) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop output resistance Rout, CL. Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop output resistance, you should instead follow the same guidance that was given for part (d) of this problem.

Image text
Consider the open-loop circuit (on the left) and closed-loop circuit (on the right) shown in Figure 1 below. In this problem, the open-loop circuit (on the left) will be used to analyze the open-loop behavior of the closed-loop circuit (on the right). closed - loof ciruit Figure 1. Open-loop (left) and closed-loop (right) circuits for Problem 1.
Here are the problem parameters:
  • The NMOS devices have g m n = 6 m A / V and r d s n = 25 k Ω .
  • The PMOS devices have g m p = 3 m A / V and r d s p = 15 k Ω .
  • Resistor values are R 1 = 1 k Ω and R 2 = 3 k Ω . a) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop gain Av. O L = V out / V in . For the purposes of this analysis, as we have done a million times before (reminder: this is the 2nd semester of electronics, so this should not be your first electronics rodeo), you should deactivate all sources in the circuit, except V in. . b) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop output resistance Rout,oL. , i.e., the resistance seen looking in at the output node V out. . You should deactivate all sources in the circuit; feel free to add an appropriate test source(s), if you think you need to do that. c) Referring to the open-loop circuit of Figure 1, determine the numerical loop gain from the test source to the output node: L G = | V out / V test | For the purposes of this analysis, you should deactivate all sources in the circuit, except V test. . Also, note that the way the loop gain is defined, it will be a positive-valued quantity. Explain why we want to use a positive loop gain for determining the closed-loop performance [see, e.g., parts (d) and (e) below]. Your answer for this part should be both i) specific to this problem and ii) generalized to any closed-loop circuit with negative feedback. You are strongly encouraged to consider incorporating a generalized block diagram to help strengthen your argument(s). d) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop gain A v , C L = V out / V in . Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop gain, you should instead utilize the results of the previous parts to determine Av,cL. Here, I need to remind you that you should do as you have been (hopefully) doing on the previous parts: first, state the equation you will use to determine A v , c L in terms of, e.g., Av.ol. and/or Rout,ol and/or LG (i.e., resist the temptation to dive straight into the numerical values, but feel free to write your equation in terms of Av,ol and/or Rout,ol. and/or LG instead of g m n , g m p , r d s n , r dpp , R 1 , R 2 ), and then plug the numbers in to your equation, and then box your numerical answer along with all the things that we have expected of your numerical quantities since day one. Make it really easy for me to find the equation you used (same story for all of the parts of this problem). e) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop output resistance Rout,CL. Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop output resistance, you should instead follow the same guidance that was given for part (d) of this problem.

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

Consider the circuit shown in Figure 2 below, with gm1 = 100 mA/V, gm2 = 20 mA/V, gm3 = 3 mA/V, R1 = 2 kΩ, R2 = 1 kΩ, VDD = 5 V, and all NMOS devices are in saturation. Channel length modulation and the body effect should be ignored for this problem. (And, hopefully, it is obvious that gm1, gm2, and gm3 correspond to the device transconductances of NMOS devices M1, M2, and M3, respectively: if this wasn't obvious, note that the next time you see something like this, I probably won't spell it out for you so explicitly. if at all, so please make a mental note of these kinds of things.) a) Determine the numerical small-signal voltage gain: i) Av = Vout/Vin in units of V/V and ii) |Av| in units of dB. Be sure to indicate whether your numerical answers are positive-valued or negative-valued (numerical answers with ambiguous signs will receive little, if any: credit, partial or otherwise). List your numerical answers in proper engineering notation format with appropriate units, and show your work. b) Determine the numerical small-signal resistance "seen" looking into node Vin. List your numerical answer in proper engineering notation format with appropriate units, and show your work. c) Determine the numerical small-signal resistance "seen" looking into node Vx. List your numerical answer in proper engineering notation format with appropriate units, and show your work. d) Determine the numerical small-signal resistance "seen" looking into node Vy. List your numerical answer in proper engineering notation format with appropriate units, and show your work. e) Determine the numerical small-signal resistance "seen" looking into node Vout. List your numerical answer in proper engineering notation format with appropriate units. and show your work.
Solution
0 0

For the circuit shown in Figure 2, VDD = 5 V, and transistors M1 and M2 have properties µnCox = 200µA/V2, (W/L) = 10, Vt0 = 0.7 V, and λ = 0. You may neglect the body effect below, unless you are specifically asked to consider it. Figure 2. Circuit for Problem 2. a) Draw the circuit above, and label the drain, gate, source, and bulk nodes for both transistors, using labels VD1, VG1, VS1, and VB1 for the drain, gate, source, and bulk nodes of device M1, respectively, and similarly for M2. In total, there should be 8 labels in your schematic. For this part, assume the transistors are in saturation. b) Determine the valid input range for the circuit under consideration; that is, determine the range on the input voltage Vin such that transistors M1 and M2 are operating in the saturation region. Note that, in your analysis, you are not constrained to Vin values between 0 V and VDD, inclusive; e.g., if Vin = 100 V keeps both of the transistors in saturation, then Vin = 100 V should be included in your range of valid input voltages. Your answer to this part should take the form Vin,low ≤ Vin ≤ Vin,high ; hopefully, it is obvious that you are being asked to provide numerical answers for the lower- and upper-bounds Vin,low and Vin,high , respectively. c) For the valid input range that you determined in part (b), determine the corresponding output voltage range; that is, determine Vout,low ≤ Vout ≤ Vout,high when the input is constrained to Vin,low ≤ Vin ≤ Vin,high. . As before, you should report numerical values for the lower- and upper-bounds Vout,low and Vout,high, , respectively. d) Determine the "on voltage" VON2 (or, as in the Sedra/Smith textbook, the "overdrive voltage") and drain current ID2 of transistor M2 over the range of valid input voltages. Also, determine the drain current ID1 of M1 over the valid input range. e) If you were to consider it, would any of the transistors in the circuit above be affected by the body effect? If "yes," then list the device (or, devices, as the case may be). Qualitatively speaking, how would your answers to parts (b) and (c) change if you were to take the body effect into account? Explain your reasoning.
Solution
0 0

For the circuit shown in Figure 1, NMOS device M1 has the following properties: kn’(W/L) = 180 μA/V2, VT0 = 2 V, λ = 0.02 V-1, γ = 0.4 V1/2, 2ϕF = 0.7 V, and ID = 10 mA. Note that capacitor Cbig is a DC blocking cap, i.e., Cbig is an open at DC and a short at all other frequencies. Figure 1. Circuit for Problem 1. a) Determine the numerical value of bias voltage Vbias which is needed to achieve a drain current of ID = 10 mA. b) Draw the small-signal equivalent circuit. c) Analyze the small-signal circuit to find Rin, Rout, and Av = Vout/Vin. Find the analytic expression for each quantity first, before determining the numerical answers. d) Recall that gmb/gm = χ. Determine the numerical value of χ for this problem. [Note that this part has nothing to do with parts (b) and (c).] e) What is the threshold voltage of device M1? [Note that this part has nothing to do with parts (b) and (c).] Show your work, list all numerical values in proper engineering notation format with appropriate units and with at least two decimal places of precision.
Solution
0 0