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Consider the SRAM cell of Figure 8.8 with a stored 0 on the left side and a stored 1 on the right side. Design the transistors of the SRAM such that node q does not exceed VTN during a read operation and node q¯ drops below VS during a write operation. The desired cell current during a read operation is 300 μA. Use 0.18 μm technology parameters. Figure 8.8 6 ST SRAM cell.

Consider the SRAM cell of Figure 8.8 with a stored 0 on the left side and a stored 1 on the right side. Design the transistors of the SRAM such that node q does not exceed VTN during a read operation and node q¯ drops below VS during a write operation. The desired cell current during a read operation is 300 μA. Use 0.18 μm technology parameters. Figure 8.8 6 ST SRAM cell.

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Consider the SRAM cell of Figure 8.8 with a stored 0 on the left side and a stored 1 on the right side. Design the transistors of the SRAM such that node q does not exceed V T N during a read operation and node q ¯ drops below V S during a write operation. The desired cell current during a read operation is 300 μ A . Use 0.18 μ m technology parameters. Figure 8.8 6 ST SRAM cell.

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