D *14.8 It is required to design a minimum-area pseudoNMOS inverter wi

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D *14.8 It is required to design a minimum-area pseudoNMOS inverter with equal high and low noise margins using a 2.5−V supply and devices for which |Vt| = 0.5 V, kn′ = 4 kp′ = 120 μA/V2, and the minimum-size device has (W/L) = 1. Use r = 3.2 and show that NML≃NMH. Specify the values of (W/L)n and (W/L)p. What is the static power dissipated in this gate? What is the ratio of propagation delays for low-to-high and high-to-low transitions? For an equivalent load capacitance of 0.1 pF, find tPLH, tPHL, and tP. At what frequency of operation would the static and dynamic power levels be equal? Is this speed of operation possible in view of the tP value you found?

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D *14.8 It is required to design a minimum-area pseudoNMOS inverter with equal high and low noise margins using a

2.5 - V

supply and devices for which

| V_{t} | = 0.5 V

k_{n}^{'} = 4 k_{p}^{'} = 120 μ A / V^{2}

, and the minimum-size device has

(W / L) = 1

. Use

r = 3.2

and show that

N M_{L} ≃ N M_{H}

. Specify the values of

(W / L)_{n}

and

(W / L)_{p}

. What is the static power dissipated in this gate? What is the ratio of propagation delays for low-to-high and high-to-low transitions? For an equivalent load capacitance of