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D 15.21 For the 6 T SRAM of Fig. 15.12, fabricated in a 0.18−μm CMOS process for which VDD = 1.8 V, Vt0 = 0.5 V, 2ϕf = 0.8 V, and γ = 0.3 V1/2, find the maximum ratio (W/L)5 /(W/L)1 for which VQ ≤ Vt0 during a read-1 operation (Fig. 15.13). Take into account the body effect in Q5. Compare to the value obtained without accounting for the body effect. figure 15.12 A CMOS SRAM memory cell.

D 15.21 For the 6 T SRAM of Fig. 15.12, fabricated in a 0.18−μm CMOS process for which VDD = 1.8 V, Vt0 = 0.5 V, 2ϕf = 0.8 V, and γ = 0.3 V1/2, find the maximum ratio (W/L)5 /(W/L)1 for which VQ ≤ Vt0 during a read-1 operation (Fig. 15.13). Take into account the body effect in Q5. Compare to the value obtained without accounting for the body effect. figure 15.12 A CMOS SRAM memory cell.

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D "15.21 For the 6T SRAM of Fig. 15.12, fabricated in a 0.18 − μ m CMOS process for which V D D = 1.8 V , V t 0 = 0.5 V , 2 ϕ f = 0.8 V , and γ = 0.3 V 1 / 2 , find the maximum ratio ( W / L ) 5 / ( W / L ) 1 for which V Q ≤ V t 0 during a read-1 operation (Fig. 15.13). Take into account the body effect in Q 5 . Compare to the value obtained without accounting for the body effect. =igure 15.12 A CMOS SRAM memory cell.

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D 16.20 Consider a 6 T SRAM cell fabricated in a 0.18−μm CMOS process for which Vtn = |Vtp| = 0.5 V and VDD = 1.8 V. If during a read-1 operation it is required that VQ¯ not exceed 0.2 V, use the graph in Fig. 16.14 to determine the maximum allowable value of the ratio (W/L)5/(W/L)1. For L1 = L5 = 0.18 μm, select values for W1 and W5 that minimize the combined areas of Q1 and Q5. Assume that the minimum width allowed is 0.18 μm.
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16.16 Repeat Exercise 16.4 for an SRAM fabricated in a 0.25−μm CMOS process for which VDD = 2.5 V and Vt = 0.5 V. EXERCISE 16.4 Find the maximum allowable W/L for the access transistors of the SRAM cell in Fig. 16.12 so that in a read operation, the voltages at Q and Q¯ do not change by more than |Vt|. Assume that the SRAM is fabricated in a 0.18−μm technology for which VDD = 1.8 V, Vtx = |Vφ| = 0.5 V and that (W/L)n = 1.5. Ans. (W/L)a ≤ 2.5 Figure 16.12 A CMOS SRAM memory cell.
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