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D 16.20 Consider a 6 T SRAM cell fabricated in a 0.18−μm CMOS process for which Vtn = |Vtp| = 0.5 V and VDD = 1.8 V. If during a read-1 operation it is required that VQ¯ not exceed 0.2 V, use the graph in Fig. 16.14 to determine the maximum allowable value of the ratio (W/L)5/(W/L)1. For L1 = L5 = 0.18 μm, select values for W1 and W5 that minimize the combined areas of Q1 and Q5. Assume that the minimum width allowed is 0.18 μm.

D 16.20 Consider a 6 T SRAM cell fabricated in a 0.18−μm CMOS process for which Vtn = |Vtp| = 0.5 V and VDD = 1.8 V. If during a read-1 operation it is required that VQ¯ not exceed 0.2 V, use the graph in Fig. 16.14 to determine the maximum allowable value of the ratio (W/L)5/(W/L)1. For L1 = L5 = 0.18 μm, select values for W1 and W5 that minimize the combined areas of Q1 and Q5. Assume that the minimum width allowed is 0.18 μm.

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D 16.20 Consider a 6T SRAM cell fabricated in a 0.18 − μ m CMOS process for which V t n = | V t p | = 0.5 V and V D D = 1.8 V . If during a read-1 operation it is required that V Q ¯ not exceed 0.2 V , use the graph in Fig. 16.14 to determine the maximum allowable value of the ratio ( W / L ) 5 / ( W / L ) 1 . For L 1 = L 5 = 0.18 μ m , select values for W 1 and W 5 that minimize the combined areas of Q 1 and Q 5 . Assume that the minimum width allowed is 0.18 μ m .

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D 16.20 Consider a 6 T SRAM cell fabricated in a 0.18−μm CMOS process for which Vtn = |Vtp| = 0.5 V and VDD = 1.8 V. If during a read-1 operation it is required that VQ¯ not exceed 0.2 V, use the graph in Fig. 16.14 to determine the maximum allowable value of the ratio (W/L)5/(W/L)1. For L1 = L5 = 0.18 μm, select values for W1 and W5 that minimize the combined areas of Q1 and Q5. Assume that the minimum width allowed is 0.18 μm. Figure 16.14 The normalized value of Vϱ¯ versus the ratio (W/L)5/(W/L)1, for the circuit in Fig. 16.13. This graph can be used to determine the maximum value permitted for (W/L)5/(W/L)1 so that VQ¯ is kept below a desired level.
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