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D 8.42 The circuit in Fig. 8.15(a) is fabricated in the 0.18-μm CMOS process whose parameters are specified in Table K.1 (Appendix K). VDD = 1.8 V. Design the circuit to obtain a voltage gain Av = -20 V/V. Use devices of equal length L operating at I = 100 μA and |Vov| = 0.2 V. Determine the required values of VG, L, (W/L)1, and (W/L)2.

D 8.42 The circuit in Fig. 8.15(a) is fabricated in the 0.18-μm CMOS process whose parameters are specified in Table K.1 (Appendix K). VDD = 1.8 V. Design the circuit to obtain a voltage gain Av = -20 V/V. Use devices of equal length L operating at I = 100 μA and |Vov| = 0.2 V. Determine the required values of VG, L, (W/L)1, and (W/L)2.

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D 8.42 The circuit in Fig. 8.15(a) is fabricated in the 0.18-μm CMOS process whose parameters are specified in Table K.1 (Appendix K). VDD = 1.8 V. Design the circuit to obtain a voltage gain Av = -20 V/V. Use devices of equal length L operating at I = 100 μA and |Vov| = 0.2 V. Determine the required values of VG, L, (W/L)1, and (W/L)2.

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