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D 9.88 In a current-mirror-loaded differential amplifier of the form shown in Fig. 9.32(a), all transistors are characterized by k’W/L = 4 mA/V2, and ∣VA∣ = 5 V. Find the bias current I for which the gain vo/vid = 20 V/V.

D 9.88 In a current-mirror-loaded differential amplifier of the form shown in Fig. 9.32(a), all transistors are characterized by k’W/L = 4 mA/V2, and ∣VA∣ = 5 V. Find the bias current I for which the gain vo/vid = 20 V/V.

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D 9.88 In a current-mirror-loaded differential amplifier of the form shown in Fig. 9.32(a), all transistors are characterized by k’W/L = 4 mA/V2, and ∣VA∣ = 5 V. Find the bias current I for which the gain vo/vid = 20 V/V.

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D 9.88 In a current-mirror-loaded differential amplifier of the form shown in Fig. 9.31(a), all transistors are characterized by k′W/L = 4 mA/V2, and |VA| = 5 V. Find the bias current I for which the gain vo/vid = 25 V/V.

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unCox = 4*upCox = 400 uA/V^2

The differential amplifier in the figure below is fabricated in a 0.18-um CMOS technology for with unCox = 400 uA/V^2, |Vt| = 0.5 V, and |VA'| = 10 V/um. If the bias current I = 200 uA and all transistors have a channel length twice the minimum and are operating at |vov| = 0.2 V, find W/L for each of Q1, Q2, Q3, and Q4, and determine the differential voltage gain Ad. The differential amplifier of Fig. 9.12(a) is fabricated in a 0.18-um CMOS technology for which un Cox = 4upCox = 400 uA/V^2, |Vt| = 0.5 V, and |VA'| = 10 V/um.
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Please design the differential amplifier shown in Fig. P3 to meet the following specifications: (1) Two NMOS transistors are matched: μnCox = 400 μA/V2, Vtn = 0.8 V, λn = 0.02 V−1, Wn = 4⋅Wp, L = 0.2μm. Please short the BODY to the SOURCE. (2) Two PMOS transistors are matched: μpCox = 200 μA/V2, Vtp = −0.8 V, λp = 0.04 V−1, Wp = TBD, L = 0.2 μm. Please short the BODY to the SOURCE. (3) ISS = 2 mA. (4) VS ≈ 0.3 V (5) The DC voltages of both vOP and vON ≈ 3.5 V. (6) The small-signal gain Av=(vop − von)/(vip − vin) ≈ 10. (7) The differential AC sinusoidal signal, vi = (vip−vin), has 100mV amplitude and 1kHz frequency. (8) VDD = 5 V. Design procedure: (a) Design Wp, Wn(= 4⋅Wp), VB, and RD by hand-calculations. Please round the resolution of Wp and Wn to 0.1μm. (Hint: λn and λp could be zero for your hand-calculations.) (b) Verify your design by a .OP simulation. Please report DC voltages of vS, vG, vOP and vON. (c) Verify your design by a .TRAN simulation. Please find Av and attach the waveforms of vIP, vIN, vOP, and vON in the same plot.
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