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Design a 2-input CMOS Schmitt NOR gate (Draw the designed circuit and show all MOSFET sizes) that satisfies the following requirements: Input down trip voltage is equal to 2/3 VDD and input up trip is equal to 1/3 VDD Minimum input gate capacitance for each input Output drive strength is equal to a symmetrical inverter with WN/LN = 4 μm/2 μm The design should yield a reasonable propagation delay Use channel lengths of 2 μm for all MOSFETs. Assume KN′ = 40 μA/V2, KP′ = 16 μA/V2, VTN = 1 V, VTP = −1 V, and VDD = 5 V.

Design a 2-input CMOS Schmitt NOR gate (Draw the designed circuit and show all MOSFET sizes) that satisfies the following requirements: Input down trip voltage is equal to 2/3 VDD and input up trip is equal to 1/3 VDD Minimum input gate capacitance for each input Output drive strength is equal to a symmetrical inverter with WN/LN = 4 μm/2 μm The design should yield a reasonable propagation delay Use channel lengths of 2 μm for all MOSFETs. Assume KN′ = 40 μA/V2, KP′ = 16 μA/V2, VTN = 1 V, VTP = −1 V, and VDD = 5 V.

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Design a 2-input CMOS Schmitt NOR gate (Draw the designed circuit and show all MOSFET sizes) that satisfies the following requirements:
  1. Input down trip voltage is equal to 2 / 3 V D D and input up trip is equal to 1 / 3 V D D
  2. Minimum input gate capacitance for each input
  3. Output drive strength is equal to a symmetrical inverter with W N / L N = 4 μ m / 2 μ m
  4. The design should yield a reasonable propagation delay
Use channel lengths of 2 μ m for all MOSFETs. Assume K X ′ = 40 μ A / V 2 , K P ′ = 16 μ A / V 2 , V T N = 1 V ′ , V T P = − 1 V , and V D D = 5 V .

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