Design a CMOS logic gate for the function: Y = (A + B)(CD + E ). Assum

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Design a CMOS logic gate for the function: Y = (A + B)(CD + E ). Assume that there is only a capacitance CL at the output node. There are no other capacitances at other nodes. a. Draw the circuit schematic for the logic gate. Show inputs clearly and number each transistors (e.g. MN1, MN2, ... for NMOS and MP1, MP2, .. for PMOS) b. Show the paths for worst and best case delays for both tPLH and tPHL. Determine delay times in terms of Req and CL. Give distinct Req values for each transistor (RMN1, RMN2, RMP1, RMP2, etc.). c. Assume there is an inverter designed in the same process as this logic gate that has the size of (W/L)P = k for PMOS and (W/L)N = m for NMOS. In order for the CMOS gate that realizes function Y to have the same tPLH and tPHL as this inverter at the worst case delay scenario, determine the size of each PMOS and NMOS in the gate you designed in terms of k and m respectively.

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Design a CMOS logic gate for the function: $Y = \bar{(A + B) (C D + E)}$ . Assume that there is only a capacitance $C_{L}$ at the output node. There are no other capacitances at other nodes. a. Draw the circuit schematic for the logic gate. Show inputs clearly and number each transistors (e.g. MN1, MN2, ... for NMOS and MP1, MP2, .. for PMOS) b. Show the paths for worst and best case delays for both $t_{P L H}$ and $t_{P H L}$ . Determine delay times in terms of $R_{e q}$ and $C_{L}$ . Give distinct $R_{e q}$ values for each transistor $(R_{M N 1}, R_{M N 2}, R_{M P 1}, R_{M P 2}$ , etc.). c. Assume there is an inverter designed in the same process as this logic gate that has the size of $(W / L_{L} = k$ for PMOS and $(W / L)_{N} = m$ for NMOS. In order for the CMOS gate that realizes function $Y$ to have the same $t_{P L H}$ and $t_{P H L}$ as this inverter at the worst case delay scenario, determine the size of each PMOS and NMOS in the gate you designed in terms of $k$ and $m$ respectively.