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Design the amplifier of Fig. 1 using the 0.18−μm CMOS process in Table 1.5 with Ibias = 400 μA to provide a gain of 20 dB. Take all gate lengths L = 0.3 μm. Veff = 0.2 V. Estimate the resulting bandwidth when driving a 2−pF capacitive load. Fig. 1

Design the amplifier of Fig. 1 using the 0.18−μm CMOS process in Table 1.5 with Ibias = 400 μA to provide a gain of 20 dB. Take all gate lengths L = 0.3 μm. Veff = 0.2 V. Estimate the resulting bandwidth when driving a 2−pF capacitive load. Fig. 1

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Design the amplifier of Fig. 1 using the 0.18 − μ m CMOS process in Table 1.5 with I bias = 400 μ A to provide a gain of 20 d B . Take all gate lengths L = 0.3 μ m . V eff = 0.2 V . Estimate the resulting bandwidth when driving a 2 − p F capacitive load. Fig. 1

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