Design the cascode amplifier shown to obtain gm1 = 2 mA/V and Ro = 200 kohm. Use a 0.18-um technology for which Vtn = 0.5 V, V'A = 5 V/um, and k'n = 400 uA/V
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Design the cascode amplifier shown to obtain gm1 = 2 mA/V and Ro = 200 kohm. Use a 0.18-um technology for which Vtn = 0.5 V, V'A = 5 V/um, and k'n = 400 uA/V
![An NMOS amplifier is shown in Figure 1. Transistor M1 is biased in the saturation region for an amplifier application. The circuit is biased with a resistive voltage divider consisting of R1 and R2, a source degeneration resistor RS, and a load resistor RD. The drain bias current for the design is ID = 500 μA and VDS is 1.625 V. The device parameters are: L = 0.5 μm, W = 10 μm, kn′ = 200 μA/V2, Vtn = 0.5 V, and λn = 0. CMOS 0.5 u Process . op . model NMOS1 nmos (KP = 200 u, VTO = 0.5, LAMBDA = 0) ;tran20 m Figure 1: A NMOS amplifier circuit including a source degeneration resistor RS. a) Determine R1 and R2 for the specified bias point. b) Determine the value for RD for the specified bias point. c) Use the LTSPICE circuit template and verify your bias circuit design. Include a copy of the schematic and the dc operating point results (text log with node voltages and currents). [8] d) Use LTSPICE to evaluate the change in ID for a variation in the technology process parameter kn′. Evaluate the change in ID for a change of ±10% in kn′. Compare the relative change in ID with the relative change in kn′. What do you observe? Explain how the source degeneration resistor RS implements negative feedback which reduces the sensitivity of the bias point to changes in kn′. [8]](https://www.doubtrix.com/uploads/editor/9212363628QZkAUhRzqb.jpg)