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Design the folded-cascode circuit presented in the figure below to provide voltage gain of 80 dB and a unity-gain frequency of 20 MHz when CL = 10 pF. Design for IB = I, and operate all devices at the same |VOV|. Utilize transistors for which |VA| is specified to be 12 V. Find the required overdrive voltages and bias currents. What slew rate is achieved? Also, for the 0.25−μm CMOS technology of Appendix K in which and kp = 93 μA/V2, specify the required W/L of each of the 11 transistors used.

Design the folded-cascode circuit presented in the figure below to provide voltage gain of 80 dB and a unity-gain frequency of 20 MHz when CL = 10 pF. Design for IB = I, and operate all devices at the same |VOV|. Utilize transistors for which |VA| is specified to be 12 V. Find the required overdrive voltages and bias currents. What slew rate is achieved? Also, for the 0.25−μm CMOS technology of Appendix K in which and kp = 93 μA/V2, specify the required W/L of each of the 11 transistors used.

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Design the folded-cascode circuit presented in the figure below to provide voltage gain of 80 d B and a unity-gain frequency of 20 M H z when C L = 10 p F . Design for I B = I , and operate all devices at the same | V O V | . Utilize transistors for which | V A | is specified to be 12 V . Find the required overdrive voltages and bias currents. What slew rate is achieved? Also, for the 0.25 − μ m CMOS technology of Appendix K in which and k p = 93 μ A / V 2 , specify the required W / L of each of the 11 transistors used.

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