Ex 4.13: For the circuit shown in Figure 4.45(a), assume transistor parameters of VTN = +0.5 V, VTP = −0.5 V, kn′ = 80 μA/V2, kp′ = 40 μA/V2, and λn = λp = 0.015 V−1. Assume IBias = 0.1 mA. Assume M2 and M3 are matched. Find the width-to-length ratio of M1 such that the small-signal voltage gain is Av = −250. (Ans. (W/L)1 = 35.2)

Ex 4.13: For the circuit shown in Figure 4.45(a), assume transistor parameters of VTN = +0.5 V, VTP = −0.5 V, kn′ = 80 μA/V2, kp′ = 40 μA/V2, and λn = λp = 0.015 V−1. Assume IBias = 0.1 mA. Assume M2 and M3 are matched. Find the width-to-length ratio of M1 such that the small-signal voltage gain is Av = −250. (Ans. (W/L)1 = 35.2)

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Ex 4.13: For the circuit shown in Figure 4.45(a), assume transistor parameters of V T N = + 0.5 V , V T P = 0.5 V , k n = 80 μ A / V 2 , k p = 40 μ A / V 2 , and λ n = λ p = 0.015 V 1 . Assume I Bias = 0.1 mA . Assume M 2 and M 3 are matched. Find the width-to-length ratio of M 1 such that the small-signal voltage gain is A v = 250 . (Ans. ( W / L ) 1 = 35.2 )

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