Question

Notify Me Bookmark

Examine the circuit below: a) Given that for the D flip flops: Setup time = .5ns Hold time = .3 ns Tcq ranges from .6 ns to 1.2 ns and the following delays: AND gates = 1 ns XOR gates = 1.5 ns NOT gates = .7 ns How fast can the circuit be clocked? b) Does the circuit satisfy hold time constraints? c) If so, modify skew values in a way that would violate hold times. Otherwise, modify skew values to meet hold times.

Examine the circuit below: a) Given that for the D flip flops: Setup time = .5ns Hold time = .3 ns Tcq ranges from .6 ns to 1.2 ns and the following delays: AND gates = 1 ns XOR gates = 1.5 ns NOT gates = .7 ns How fast can the circuit be clocked? b) Does the circuit satisfy hold time constraints? c) If so, modify skew values in a way that would violate hold times. Otherwise, modify skew values to meet hold times.

Image text
Examine the circuit below: a) Given that for the D flip flops: Setup time = .5 n s Hold time = .3 n s T c q ranges from .6 ns to 1.2 ns and the following delays: AND gates = 1 n s XOR gates = 1.5 n s NOT gates = .7 n s How fast can the circuit be clocked? b) Does the circuit satisfy hold time constraints? c) If so, modify skew values in a way that would violate hold times. Otherwise, modify skew values to meet hold times.

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

Consider the following circuit Inverter timing: Propagation delay tp = 20 pS Flip-Flop timing: Setup time tsu = 30 pS Hold time thold = 10 ps Clock-to-Q delay tclk- = 50 pS Assume the CLK signal has a square waveform with 50% duty cycle. a. Draw the waveforms of signals CLK, D, and Q for 4 clock cycles. b. What is the ratio between the oscillation frequency of the signals CLK and Q ? c. For this circuit to operate correctly, determine the maximum CLK frequency based on the given timing characteristics of the flip-flop and the inverter. d. Would a hold time violation occur on the flip-flop at any CLK frequency? Why or why not? e. If this circuit dissipates 100 Micro-Watts when operating at Vdd = 2.5 Volts and CLK frequency of 1 GHz, estimate the power dissipation of the circuit when operating at Vdd = 1.25 V and CLK frequency of 100 MHz. Assume the power dissipation is dominated by the switching (dynamic) power. (1 GHz = 109 Hz and 1 MHz = 106 Hz)
Solution
0 0

Consider the CMOS inverter circuit with a capacitor connected at its output as shown below. Here Kn′ = 2 mA/V2 and VTn = 1.5 V, Kp′ = 1 mA/V2 and VTp = −0.5 V, all MOSFETs have L = 1 μm, and remember that K = K′(W/L). For a MOSFET in triode, use the S-R model with RON = 1 /K(|VGS| − |VT| ) (works for both nFET and pFET). a) Design Wp and Wn such that the overall circuit threshold, VTH, occurs at VDD/2 as shown in the graph. Here you can assume that at the threshold point VIN = VOUT = VTH. Use the smallest integer values you can for Wp and Wn, assuming the minimum width allowed is 1 μm. b) When VIN = VDD, draw the equivalent circuit. What is the time constant? c) When VIN = 0, draw the equivalent circuit. What is the time constant? d) Based on your answers from (b) and (c), which transition do you expect to be fastest: when vOUT transitions from VDD to 0 V, or when vOUT transitions from 0 V to VDD ? Why?
Solution
0 0

For the following figure, all the D flip-flops have setup time as 2 ns, hold time as 4 ns, tclk-a-min = 9 ns and tclk-q-m-max = 11 ns. a) Assuming clock period as 25 ns, determine (by using setup equation) if the circuit has setup violation. If there is set up violation, what should be the value of clock period to avoid setup violation. b) Determine (by using hold time equation), if the circuit has hold time violation. [4] c) Modify (and redraw) the circuit without removing any buffers, such that it works at clock period of 25 ns and does not have any timing violations. (Assume only two buffers, with min delay of 6 ns and max delay of 8 ns, are available). Show clear steps/methodology used for arriving at the violation free circuit. [12]
Solution
0 0