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Figure 1 shows a network of logic gates driving a load capacitance CL. The value of CL is 20+ the final two digits of your URN. (i) Find the normalised delay D. Show clearly your calculations. (ii) Select the sizes of gates x and y to minimise the delay from A to B along the path indicated.

Figure 1 shows a network of logic gates driving a load capacitance CL. The value of CL is 20+ the final two digits of your URN. (i) Find the normalised delay D. Show clearly your calculations. (ii) Select the sizes of gates x and y to minimise the delay from A to B along the path indicated.

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Figure 1 shows a network of logic gates driving a load capacitance CL. The value of CL is 20+ the final two digits of your URN. (i) Find the normalised delay D. Show clearly your calculations. (ii) Select the sizes of gates x and y to minimise the delay from A to B along the path indicated.

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