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Figure 4: Circuit Diagram for Q.3 For the circuit diagram in Figure 4, the NMOS and PMOS were fabricated in a process where μnCox = 120 μA/V2, μpCox = 60 μA/V2, Vtn = −Vtp = 1 V. (a) Find the value of the voltage marked at Vy (b) Determine the width ratio of NMOS and PMOS of the inverter when Vinv = (Vy -0.5)V. (c) Given, VOL = 0 V and VOH = 5 V for the inverter shown in the circuit. Identify the High and Low Noise Margins for an inverter added after Vout which has VIH = 3.9 V and VIL = 1.2 V.

Figure 4: Circuit Diagram for Q.3 For the circuit diagram in Figure 4, the NMOS and PMOS were fabricated in a process where μnCox = 120 μA/V2, μpCox = 60 μA/V2, Vtn = −Vtp = 1 V. (a) Find the value of the voltage marked at Vy (b) Determine the width ratio of NMOS and PMOS of the inverter when Vinv = (Vy -0.5)V. (c) Given, VOL = 0 V and VOH = 5 V for the inverter shown in the circuit. Identify the High and Low Noise Margins for an inverter added after Vout which has VIH = 3.9 V and VIL = 1.2 V.

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Figure 4: Circuit Diagram for Q. 3
For the circuit diagram in Figure 4, the NMOS and PMOS were fabricated in a process where μ n C o x = 120 μ A / V 2 , μ p C 0 κ = 60 μ A / V 2 , V t n = − V t p = 1 V .

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For the circuit diagram in Figure 4, the NMOS and PMOS were fabricated in a process where μnCox = 120 μA/V2, μpCox = 60 μA/V2, Vtn = −Vtp = 1 V. (a) Find the value of the voltage marked at Vy. (b) Determine the width ratio of NMOS and PMOS of the inverter when Vinv = (Vy−0.5)V. (c) Given, VOL = 0 V and VOH = 5 V for the inverter shown in the circuit. Identify the High and Low Noise Margins for an inverter added after Vout which has VIH = 3.9 V and VIL = 1.2 V.
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