Figure Q1(b) shows a single-stage amplifier driving a load of RL and CL. VBIAS and IDC are DC bias voltage and current of the transistor Q1, respectively. By considering the internal capacitive effect of Q1, analyse the circuit using high-frequency small-signal model to obtain the pole frequencies of the circuit, assuming the Early effect is neglected. [10 Marks] Figure Q1(b)

Figure Q1(b) shows a single-stage amplifier driving a load of RL and CL. VBIAS and IDC are DC bias voltage and current of the transistor Q1, respectively. By considering the internal capacitive effect of Q1, analyse the circuit using high-frequency small-signal model to obtain the pole frequencies of the circuit, assuming the Early effect is neglected. [10 Marks] Figure Q1(b)

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Figure Q1(b) shows a single-stage amplifier driving a load of R L and C L . V B I A S and I D C are DC bias voltage and current of the transistor Q 1 , respectively. By considering the internal capacitive effect of Q 1 , analyse the circuit using high-frequency small-signal model to obtain the pole frequencies of the circuit, assuming the Early effect is neglected. [10 Marks] Figure Q1(b)

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