Question

Notify Me Bookmark

Find VX for the following circuit if (i) γ = 0 (ii) γ = 0.4V1/2 . Take β = 200 μA/V2; VTo = 1V; |2ϕF| = 0.6 V. Neglect channel length modulation.

Find VX for the following circuit if (i) γ = 0 (ii) γ = 0.4V1/2 . Take β = 200 μA/V2; VTo = 1V; |2ϕF| = 0.6 V. Neglect channel length modulation.

Image text
Find VX for the following circuit if (i) γ = 0 (ii) γ = 0.4V1/2 . Take β = 200 μA/V2; VTo = 1V; |2ϕF| = 0.6 V. Neglect channel length modulation.

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

Problem 2.1: The N-channel enhancement type MOSFET in the following circuit has kn′ = 200 μA/V2, W/L = 20 /0.18, Vt = 0.6 V and λ = 0.1 V−1. Find the mode of its operation and the drain current in the following cases: (i) VG = 1 V and VD = 0.2 V and (ii) VG = 1 V and VD = 2 V. Key formulae: Cut-off condition VGS < Vt; current ID = 0 Linear region conditions VGS > Vt and VGD > Vt; current ID = kn′WL[(VGS − Vt)VDS − 12 VDS2] Saturation conditions VGS > Vt and VGD < Vt; current ID = 12 kn′WL(VGS − Vt)2(1 + λVDS) Solution: Case (i) VGS = and VGD = hence the mode of operation is ID = Problem 2.2: What is the mode of operation of the transistor in each of the following circuits? Take Vt = −0.8 V Note: Identify the type of the MOSFET transistor and take into account the change of the sign for all the voltages when you check the conditions for cut-off, linear mode and saturation. Solution:
Solution
0 0

The MOS transistors have the following characteristics: nMOS:Vtn = 0.7 V, Kn′ = 200 μA/V2. Assume VDD = 5 V. The required current ID1 = 100 μA the output voltage ( Vout) should be allowed to swing to a low of 0.2 V and the DC value of VOUT = 2.5 volts. Also design for current IREF = 50 μA. (a) Find the (W/L) ratio of all transistors and (ii) the resistor R. For this part you may assume there is no channel length modulation. ( 25 points). (b) Show a clean and labeled small signal equivalent circuit with the values shown. Assume all transistors have |λ| = 0.02 V1 (10 points) (c) Find both an expression and the numerical value for the small signal gain vo/vin, and Rout . 15 points)
Solution
0 0

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.
Solution
0 0