Flip-Flops and Timing Diagrams (15 points) Complete the timing diagram for the specified flip-flop such that the output Q will be as indicated. Assume that the input signal can change only on the vertical lines. Also, assume that the setup time tsu and the hold time th are each equal to the width of one square. a) Complete the timing diagram for the D input to a negative-edge triggered D flip-flop. b) Complete the timing diagram for the T input to a negative-edge triggered T flip-flop. c) Complete the timing diagram for the J input to a negative-edge triggered JK flip-flop.
![For the following figure, all the D flip-flops have setup time as 2 ns, hold time as 4 ns, tclk-a-min = 9 ns and tclk-q-m-max = 11 ns. a) Assuming clock period as 25 ns, determine (by using setup equation) if the circuit has setup violation. If there is set up violation, what should be the value of clock period to avoid setup violation. b) Determine (by using hold time equation), if the circuit has hold time violation. [4] c) Modify (and redraw) the circuit without removing any buffers, such that it works at clock period of 25 ns and does not have any timing violations. (Assume only two buffers, with min delay of 6 ns and max delay of 8 ns, are available). Show clear steps/methodology used for arriving at the violation free circuit. [12]](https://www.doubtrix.com/uploads/editor/8257480979SjIoyUPhkx.jpeg)