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For a 2 input NOR gate, what is the worst case falling delay with a fan-out of 1? (worst case is when only one of the nMOS transistors is ON) 6RC 15RC 11RC 9RC

For a 2 input NOR gate, what is the worst case falling delay with a fan-out of 1? (worst case is when only one of the nMOS transistors is ON) 6RC 15RC 11RC 9RC

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For a 2 input NOR gate, what is the worst case falling delay with a fan-out of 1 ? (worst case is when only one of the nMOS transistors is ON) 6RC 15RC 11RC 9RC

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Charge sharing is an important problem in dynamic circuits. Switching exposes a fixed amount of charge to a different capacitive environment. This results in node voltage change. After pre-charge stage, the output node voltage of the dynamic logic circuit in Figure 1 will be equal to VDD. During the evaluate phase, assume A = 1 and B=0. Output node will not connect to ground but the total charge on the output node (Q = C.V) will be shared by parasitic capacitance (C1) and the load capacitance (CL). So that the output voltage will drop and be equal to M1 source voltage. a. The circuit is Figure 1 is pre-charged with VDD = 3V. During evaluation stage, M1 turns on and M2 is off (A=1 and B=0). CL = 250fF, C1 = 125fF and Vt0,n=0.55V. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? b. Repeat question a for C1 = 40fF. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? If not, what is the value of the output voltage at this scenario? c. With A = 1 and B = 0, the output of the circuit in Fig 1 should be logic high. However, you have seen that logic high does not mean VDD for this example. Output voltage depends on the parasitic capacitance at the source node of M2. For a dynamic 2 input NAND gate, what is the maximum value that the Figure 1 output voltage can reach when A= 1 and B = 0?

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Problem 1: Consider the logic circuit below to the left: (a) What is the logic function implemented by the design below? (b) Size NMOS and PMOS devices in the circuit below so that the worst-case pull-up and pull-down strength of the circuit is exactly as much as in the inverter shown to the right. Assume that all the transistors in the circuit above and in the inverter have a minimum channel length (LMIN). In the inverter, the width of NMOS is WMIN and PMOS is 2×WMN. (c) For the logic design, identify the transition for the worst case 'high to low' and 'low to high' delay considering that only one of the input (among A, B, C) switches. Compute RC delay for these transitions. Assume that the resistance of a minimum width width (WMIN), the junction capacitance is C at each source and drain ends. Ignore any external load capacitance for the circuit.

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P R O B LEM II. 6 a) Express F¯ in a simplified sum-of-products form given that F = AB¯+CD¯. b) Implement the logic function F = AB¯+CD¯ with an NMOS digital logic circuit that obeys the static discipline defined by the low-level and high-level logic thresholds VIL = VOL = VL and VIH = VOH = VH, respectively. Assume the supply voltage is VS, and that the on-state resistance of the NMOS transistors is RON. Determine the lowest value of the pull-up resistor RPU for which the circuit will obey the static discipline in terms of RON, VS, VL, and VH; not all variables need appear in your answer. c) Implement the logic function F = AB¯+CD¯ with a CMOS digital logic circuit. (Hint: make use of the result from part (a). ) d) Suppose that the NMOS and CMOS circuits above drive a capacitance CL. Assume that the on-state resistance of both the PMOS and NMOS transistors is RON. For both the NMOS and CMOS circuits determine the worst-case output rise time. For the purpose of this problem, assume that the worst-case output rise time is the time the output takes to go from 0 V to VH. Sketch the form of the output for both the NMOS and the CMOS circuit. e) Suppose that the inputs are arranged such that B = 1, C = 0, and D = 1, and that a 0−V to 5−V square-wave signal is applied to the input A. Assume the square wave cycle time is T, and that T is large enough so that the output comes close to its steady state value for both falling and rising transitions. Under these conditions, compute the power consumed by the CMOS and NMOS circuits when driving the capacitance CL load.
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