For a CMOS inverter fabricated in a 65nm process with VDD = 1.0 V, Vtn

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For a CMOS inverter fabricated in a 65nm process with VDD = 1.0 V, Vtn = Vtp = 0.35 V, K′n = K′p = 500 A/V2, and having (W/L)n and (W/L)p = 4. Find TPHL, TPLH, and TP, when the equivalent load capacitance C = 4 fF. Use the method of average currents. Now, create a NAND gate with worst-case pull-up and pull-down that match the current drive of the inverter. Calculate the worst and best case delays with equivalent load capacitance C = 4 fF. Use the method of average currents.

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For a CMOS inverter fabricated in a $65 n m$ process with $V_{D D} = 1.0 V, V t n = V t p = 0.35 V$ , $K^{'} n = K^{'} p = 500 A / V^{2}$ , and having $(W / L) n$ and $(W / L) p = 4$ . Find $T_{P H L}, T_{P L H}$ , and $T_{P}$ , when the equivalent load capacitance $C = 4 f F$ . Use the method of average currents. Now, create a NAND gate with worst-case pull-up and pull-down that match the current drive of the inverter. Calculate the worst and best case delays with equivalent load capacitance $C = 4 f F$ . Use the method of average currents.