For a PMOS transistor kp = 80 μA V2, and Vtp = −1.5 V. The gate is tie

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For a PMOS transistor kp = 80 μA V2, and Vtp = −1.5 V. The gate is tied to ground and Vs = 5 V. Determine the mode of operation (triode or saturation) and calculate the drain current ID for VD = 4 Volts and VD = 1.5 Volts (For VD = 4 V, ID = 240 μA; for VD = 1.5 V, ID = 490 μA ) Note that when VD = 1.5 V, the transistor is right on the line between the triode and saturation regions, so either equation for ID will give you the same value of ID.)

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For a PMOS transistor

k_{p} = 80 \frac{μ A}{V^{2}}

, and

V_{t p} = - 1.5 V

. The gate is tied to ground and

V_{s} = 5 V

. Determine the mode of operation (triode or saturation) and calculate the drain current

I_{D}

for

V_{D} = 4

Volts and

V_{D} = 1.5

Volts

(For V_{D} = 4 V, I_{D} = 240 μ A; for V_{D} = 1.5 V, I_{D} = 490 μ A)

Note that when

V_{D} = 1.5 V

, the transistor is right on the line between the triode and saturation regions, so either equation for

I_{D}

will give you the same value of

I_{D}

.)

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Figure P7.33 shows a discrete-circuit amplifier. The input signal vsig is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite). All capacitors behave as short circuits for signals and as open circuits for dc. (a) If the transistor has Vt = 1 V, and kn = 4 mA/V2 , verify that the bias circuit establishes VGS = 1.5 V, ID = 0.5 mA, and VD = +7.0 V. That is, assume these values, and verify that they are consistent with the values of the circuit components and the device parameters. (b) Find gm and ro if VA = 100 V. (c) Draw a complete small-signal equivalent circuit for the amplifier, assuming all capacitors behave as short circuits at signal frequencies. (d) Find Rin, vgs/vsig, vo/vgs, and vo/vsig.

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