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For the circuit given below, determine the value of R so that two noise margin values become equal to each other. Calculate the noise margins with your design.

For the circuit given below, determine the value of R so that two noise margin values become equal to each other. Calculate the noise margins with your design.

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For the circuit given below, determine the value of R so that two noise margin values become equal to each other. Calculate the noise margins with your design.

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For the two-stage OTA below, assume that Iref = 50 μA and that all transistors are designed for |Veff|= 0.2 V. Assume: |Vt|= 0.5 V for all devices, Vdd = 3 V, M5 and M7 are 2X larger than M8, λ = 0.2V-1. 1. Calculate the total power consumption of this OTA. 2. Complete the table below for the small-signal parameters of all transistors. Transistors Ids Veff gm gds ro μf 3. What is the gain of this OTA in dB? 4. What is the CMRR of this OTA in dB? 5. What is the common-mode input range of the circuit? 6. What is the output swing of this OTA? 7. Assume that this OTA has parasitic capacitances C1 = C2 = 100fF, where C1 is the total shunt capacitance at output of stage 1 and C2 is the same for stage 2. What value of Cc is needed to set the gain-bandwidth product equal to the second-pole location (resulting in 45-deg phase margin)? 8. For this value of Cc, calculate the GBW (in MHz, careful of the 2π ) and slew rate (in V/us), where slew rate is defined as 9. What value of RZ is needed to set the zero location to the LHP at 1.7X the GBW value? 10. For the values you have selected in Table 1, will this OTA have any systematic offset? Why or why not?

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Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].

Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].
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Part 1: Design of a CMOS Inverter Objective: Design a CMOS inverter so as to achieve a given performance specification. Figure 1. CMOS Inverter Consider a CMOS inverter such as the one shown in Figure 1. For the NMOS driver, use VT0 = 0.4 V, kn′ = 432 μA/V2, 2ϕF∣ = 0.88 V, γ = 0.2 V1 /2, λ = 0 V−1, Wn = 25 μm, and Ln = 0.1 μm. For the PMOS load, use VT0 = −0.4 V, kp′ = 108 μA/V2, |2ϕF| = 0.88 V, γ = 0.2 V1 /2, λ = 0 V−1, and Lp = 0.1 μm. ⇒ Design the inverter - i. e. , determine the value of Wp for the PMOS load - so as to make the noise margins equal: NML = NMH. In order to limit calculation complexity while still obtaining a reasonably accurate estimate, use the long-channel equations for NMOS and PMOS devices calculations. Round your calculated value of Wp to the nearest multiple of 0.05 μm. ⇒ Using your rounded value for Wp, calculate the expected value for the switching threshold, Vth. ⇒ Lastly, double the rounded value of Wp, then calculate the revised value of the switching threshold, Vth . Comment on the effect of decreasing the ratio KR = kdriver kload .

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