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For the circuit in Fig. 3 assume VDD = 2.6 V, Ibias, and the bias voltage, Vbias, are; a) 0.9 mA, 1.25 V b) 9 μA, 1.1 V c) 9 μA, 1.0 V d) 90 μA, 1.0 V e) None of the above Fig. 3 CMOS Bias Circuit

For the circuit in Fig. 3 assume VDD = 2.6 V, Ibias, and the bias voltage, Vbias, are; a) 0.9 mA, 1.25 V b) 9 μA, 1.1 V c) 9 μA, 1.0 V d) 90 μA, 1.0 V e) None of the above Fig. 3 CMOS Bias Circuit

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( 7 p t s ) 2) For the circuit in Fig. 3 assume V D D = 2.6 V , 1 Ibias, and the bias voltage, Vbias, are; a) 0.9 m A , 1.25 V b) 9 μ A , 1.1 V c) 9 μ A , 1.0 V d) 90 μ A , 1.0 V e) None of the above Fig. 3 CMOS Bias Circuit

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