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For the circuit on the left, KN = KP, Vtn = 1 V, Vtp = -1 V Find the range of bias voltage Vb, to keep M1 in SATURATION and M2 in TRIODE for a. VI = 2 V b. VI = 3 V

For the circuit on the left, KN = KP, Vtn = 1 V, Vtp = -1 V Find the range of bias voltage Vb, to keep M1 in SATURATION and M2 in TRIODE for a. VI = 2 V b. VI = 3 V

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For the circuit on the left, KN = KP, Vtn = 1 V, Vtp = -1 V Find the range of bias voltage Vb, to keep M1 in SATURATION and M2 in TRIODE for a. VI = 2 V b. VI = 3 V

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The PMOS transistor shown in Fig. E5.7 has Vtp = -1 V, kp' = 60 uA/V^2, and W/L = 10 (a) Find the range of VG for which the transistor conducts. (b) In terms of VG, find the range of VD for which the transistor operates in the triode region. (c) In terms of VG, find the range of VD, for which the transistor operates in saturation. (d) Neglecting channel-length modulation (i.e., assuming lambda =0), find the values of |Vov| and VG and the corresponding range of VD to operate the transistor in the saturation mode with ID = 75 uA. (e) If lambda = -0.02 V-1, find the value of ro corresponding to the overdrive voltage determined in (d). (f) For lambda = - 0.02 V-1 and for the value of Vov determined in (d), find ID, at VD = +3 V and at VD = 0 V; hence, calculate the value of the apparent output resistance in saturation. Compare to the value found in (e).
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The MOS transistors have the following characteristics: Vtn = |Vtp| = 0.5 V, Kn’ = 400 µA/V2 and Kn’ = 100 µA/V2. Assume VDD = 3 V and Q2 and Q3 are matched. The required gm of the amplifying transistor (Q1) is 1000 µA/V and the output voltage (VOUT ) should be allowed to swing to within 0.2 V of VDD. (a) Find the (W/L) ratio of all transistors and the resistor R. For this part you may assume there is no channel length modulation. (b) Show a clean and labeled small signal equivalent circuit with the values (gm and ra) shown. Assume all transistors have |λ| = 0.02 V-1 (c) Find both an expression and the numerical value for the small signal gain v0/vsig, and Rout. (d) What is the range of the output voltage swing.
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Part 1: Hand Calculation Consider the following circuit with the following parameters: • Load: is a depletion NMOS, VT(load) = -1 V, kn0 = 100uA/V2 ,( W/L)Load = 6 • Driver: is an enhancement NMOS with VT(driver) = 0.5 V, kn0 = 100uA/V2 ,( W/L)driver = 4 • VDD = 3 V Neglect body effect and calculate: a) vO for vI = 0 V and vI = 1 V b) vo for vI = 2 V and vI = 3 V c) The transition point for the load transistor d) The transition point for the driver transistor e) The point where vO = vI f) Sketch the voltage transfer characteristics (VTC) indicating the points calculated before Part 2: Simulation Draw the circuit on LTSpice and use the part nmos 4 connecting its body terminal to its source, with parameters as in Part 1 (note that in LTSpice, the parameter kn’ is called kp and the parameter VT is called VTO, and you can set W/L by right clicking on the transistor). a) Draw the VTC, and Verify the results of part 1 b) Repeat the simulation with (W/L)driver = 8, • find the point where vO = vI from the VTC • how does increasing (W/L) driver of the affect the VTC ? Notes: • Homework submission is through the Moodle platform • Submit a single compressed file containing: • The hand calculations • Screenshot showing the circuit and the simulation results • The schematic file (.asc) • The netlist file (.net)

 
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