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For the circuits shown in Fig. 1, plot Vo1, Vo2, Vo3, and Vo. Period of the clock is 20 ns. Device resistance is less than 1 kΩ for VGS > VTH and VTH = 0.5 V. Vo1, Vo2, Vo3, and Vo are loaded with capacitance of 0.1 pF. Vdd = 2 V. [9+6] (a) (b)

For the circuits shown in Fig. 1, plot Vo1, Vo2, Vo3, and Vo. Period of the clock is 20 ns. Device resistance is less than 1 kΩ for VGS > VTH and VTH = 0.5 V. Vo1, Vo2, Vo3, and Vo are loaded with capacitance of 0.1 pF. Vdd = 2 V. [9+6] (a) (b)

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  1. For the circuits shown in Fig. 1, plot V ol , V ol V os , and V o . Period of the clock is 20 ns . Device resistance is less than 1 k Ω for VGS > VTH and VTH = 0.5 V . V ol , V OI V ol , and V 。 are loaded with capacitance of 0.1 pF . Vdd = 2 V . [9+6] (a) (b)

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